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      1 /*
      2  * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
      3  * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions are met:
      7  *
      8  * Redistributions of source code must retain the above copyright notice, this
      9  * list of conditions and the following disclaimer.
     10  *
     11  * Redistributions in binary form must reproduce the above copyright notice,
     12  * this list of conditions and the following disclaimer in the documentation
     13  * and/or other materials provided with the distribution.
     14  *
     15  * Neither the name of ARM nor the names of its contributors may be used
     16  * to endorse or promote products derived from this software without specific
     17  * prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef __HI6220_REGS_PMCTRL_H__
     33 #define __HI6220_REGS_PMCTRL_H__
     34 
     35 #define PMCTRL_BASE				0xF7032000
     36 
     37 #define PMCTRL_ACPUPLLCTRL			(PMCTRL_BASE + 0x000)
     38 #define PMCTRL_ACPUPLLFREQ			(PMCTRL_BASE + 0x004)
     39 #define PMCTRL_DDRPLL1CTRL			(PMCTRL_BASE + 0x010)
     40 #define PMCTRL_DDRPLL0CTRL			(PMCTRL_BASE + 0x030)
     41 #define PMCTRL_MEDPLLCTRL			(PMCTRL_BASE + 0x038)
     42 #define PMCTRL_ACPUPLLSEL			(PMCTRL_BASE + 0x100)
     43 #define PMCTRL_ACPUCLKDIV			(PMCTRL_BASE + 0x104)
     44 #define PMCTRL_ACPUSYSPLLCFG			(PMCTRL_BASE + 0x110)
     45 #define PMCTRL_ACPUCLKOFFCFG			(PMCTRL_BASE + 0x114)
     46 #define PMCTRL_ACPUPLLFRAC			(PMCTRL_BASE + 0x134)
     47 #define PMCTRL_ACPUPMUVOLUPTIME			(PMCTRL_BASE + 0x360)
     48 #define PMCTRL_ACPUPMUVOLDNTIME			(PMCTRL_BASE + 0x364)
     49 #define PMCTRL_ACPUVOLPMUADDR			(PMCTRL_BASE + 0x368)
     50 #define PMCTRL_ACPUVOLUPSTEP			(PMCTRL_BASE + 0x36c)
     51 #define PMCTRL_ACPUVOLDNSTEP			(PMCTRL_BASE + 0x370)
     52 #define PMCTRL_ACPUDFTVOL			(PMCTRL_BASE + 0x374)
     53 #define PMCTRL_ACPUDESTVOL			(PMCTRL_BASE + 0x378)
     54 #define PMCTRL_ACPUVOLTTIMEOUT			(PMCTRL_BASE + 0x37c)
     55 
     56 #define PMCTRL_ACPUPLLCTRL_EN_CFG		(1 << 0)
     57 
     58 #define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK	(3 << 0)
     59 #define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK		(3 << 8)
     60 #define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK	(3 << 16)
     61 #define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK		(3 << 24)
     62 
     63 #define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG		(1 << 0)
     64 #define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT		(1 << 1)
     65 #define PMCTRL_ACPUPLLSEL_SYSPLL_STAT		(1 << 2)
     66 
     67 #define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK	0x7
     68 #define PMCTRL_ACPUSYSPLL_CLKEN_CFG		(1 << 4)
     69 #define PMCTRL_ACPUSYSPLL_CLKDIV_SW		(3 << 12)
     70 
     71 #define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN	(1 << 4)
     72 #define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK	(3 << 12)
     73 
     74 #define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK	0x7f
     75 #define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK	(0x7f << 8)
     76 
     77 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START   (0)
     78 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_END     (0)
     79 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_START      (2)
     80 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_END        (2)
     81 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_START     (4)
     82 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_END       (27)
     83 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START  (28)
     84 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_END    (28)
     85 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_START     (29)
     86 #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_END       (29)
     87 
     88 #define SOC_PMCTRL_ACPUPLLFRAC_ADDR(base)   ((base) + (0x134))
     89 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START   (12)
     90 
     91 #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START   (0)
     92 #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_END     (0)
     93 #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START  (1)
     94 #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_END    (1)
     95 #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START   (2)
     96 #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_END     (2)
     97 
     98 #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START     (0)
     99 #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_END       (1)
    100 #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START   (8)
    101 #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_END     (9)
    102 #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START    (16)
    103 #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_END      (17)
    104 #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START  (24)
    105 #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_END    (25)
    106 
    107 #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START   (0)
    108 #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END     (6)
    109 #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START  (8)
    110 #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_END    (14)
    111 
    112 #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START  (0)
    113 #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_END    (0)
    114 
    115 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_START      (0)
    116 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_END        (2)
    117 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START    (4)
    118 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_END      (4)
    119 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_START  (8)
    120 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_END    (9)
    121 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_START     (16)
    122 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_END       (19)
    123 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_START   (20)
    124 #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_END     (20)
    125 
    126 #endif /* __HI6220_REGS_PMCTRL_H__ */
    127