1 /************************************************************************** 2 * 3 * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN 4 * Written 2003-2003 by Timothy Legge <tlegge (at) rogers.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 * 20 * Portions of this code (almost all) based on: 21 * tlan.c: Linux ThunderLan Driver: 22 * 23 * by James Banks 24 * 25 * (C) 1997-1998 Caldera, Inc. 26 * (C) 1998 James Banks 27 * (C) 1999-2001 Torben Mathiasen 28 * (C) 2002 Samuel Chessman 29 * 30 * REVISION HISTORY: 31 * ================ 32 * v1.0 07-08-2003 timlegge Initial not quite working version 33 * 34 * Indent Style: indent -kr -i8 35 ***************************************************************************/ 36 37 FILE_LICENCE ( GPL2_OR_LATER ); 38 39 /***************************************************************** 40 * TLan Definitions 41 * 42 ****************************************************************/ 43 44 #define FALSE 0 45 #define TRUE 1 46 47 #define TLAN_MIN_FRAME_SIZE 64 48 #define TLAN_MAX_FRAME_SIZE 1600 49 50 #define TLAN_NUM_RX_LISTS 4 51 #define TLAN_NUM_TX_LISTS 2 52 53 #define TLAN_IGNORE 0 54 #define TLAN_RECORD 1 55 /* 56 #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args ); 57 */ 58 #define TLAN_DEBUG_GNRL 0x0001 59 #define TLAN_DEBUG_TX 0x0002 60 #define TLAN_DEBUG_RX 0x0004 61 #define TLAN_DEBUG_LIST 0x0008 62 #define TLAN_DEBUG_PROBE 0x0010 63 64 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */ 65 #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */ 66 67 68 /***************************************************************** 69 * Device Identification Definitions 70 * 71 ****************************************************************/ 72 73 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 74 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 75 #ifndef PCI_DEVICE_ID_OLICOM_OC2183 76 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 77 #endif 78 #ifndef PCI_DEVICE_ID_OLICOM_OC2325 79 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 80 #endif 81 #ifndef PCI_DEVICE_ID_OLICOM_OC2326 82 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 83 #endif 84 85 typedef struct tlan_adapter_entry { 86 u16 vendorId; 87 u16 deviceId; 88 char *deviceLabel; 89 u32 flags; 90 u16 addrOfs; 91 } TLanAdapterEntry; 92 93 #define TLAN_ADAPTER_NONE 0x00000000 94 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 95 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 96 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004 97 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 98 99 #define TLAN_SPEED_DEFAULT 0 100 #define TLAN_SPEED_10 10 101 #define TLAN_SPEED_100 100 102 103 #define TLAN_DUPLEX_DEFAULT 0 104 #define TLAN_DUPLEX_HALF 1 105 #define TLAN_DUPLEX_FULL 2 106 107 108 109 /***************************************************************** 110 * EISA Definitions 111 * 112 ****************************************************************/ 113 114 #define EISA_ID 0xc80 /* EISA ID Registers */ 115 #define EISA_ID0 0xc80 /* EISA ID Register 0 */ 116 #define EISA_ID1 0xc81 /* EISA ID Register 1 */ 117 #define EISA_ID2 0xc82 /* EISA ID Register 2 */ 118 #define EISA_ID3 0xc83 /* EISA ID Register 3 */ 119 #define EISA_CR 0xc84 /* EISA Control Register */ 120 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */ 121 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */ 122 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */ 123 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */ 124 #define EISA_APROM 0xc90 /* Ethernet Address PROM */ 125 126 127 128 /***************************************************************** 129 * Rx/Tx List Definitions 130 * 131 ****************************************************************/ 132 133 #define TLAN_BUFFERS_PER_LIST 10 134 #define TLAN_LAST_BUFFER 0x80000000 135 #define TLAN_CSTAT_UNUSED 0x8000 136 #define TLAN_CSTAT_FRM_CMP 0x4000 137 #define TLAN_CSTAT_READY 0x3000 138 #define TLAN_CSTAT_EOC 0x0800 139 #define TLAN_CSTAT_RX_ERROR 0x0400 140 #define TLAN_CSTAT_PASS_CRC 0x0200 141 #define TLAN_CSTAT_DP_PR 0x0100 142 143 144 145 146 147 148 /***************************************************************** 149 * PHY definitions 150 * 151 ****************************************************************/ 152 153 #define TLAN_PHY_MAX_ADDR 0x1F 154 #define TLAN_PHY_NONE 0x20 155 156 157 158 /***************************************************************** 159 * TLan Driver Timer Definitions 160 * 161 ****************************************************************/ 162 163 #define TLAN_TIMER_LINK_BEAT 1 164 #define TLAN_TIMER_ACTIVITY 2 165 #define TLAN_TIMER_PHY_PDOWN 3 166 #define TLAN_TIMER_PHY_PUP 4 167 #define TLAN_TIMER_PHY_RESET 5 168 #define TLAN_TIMER_PHY_START_LINK 6 169 #define TLAN_TIMER_PHY_FINISH_AN 7 170 #define TLAN_TIMER_FINISH_RESET 8 171 172 #define TLAN_TIMER_ACT_DELAY (HZ/10) 173 174 175 176 177 /***************************************************************** 178 * TLan Driver Eeprom Definitions 179 * 180 ****************************************************************/ 181 182 #define TLAN_EEPROM_ACK 0 183 #define TLAN_EEPROM_STOP 1 184 185 186 187 188 /***************************************************************** 189 * Host Register Offsets and Contents 190 * 191 ****************************************************************/ 192 193 #define TLAN_HOST_CMD 0x00 194 #define TLAN_HC_GO 0x80000000 195 #define TLAN_HC_STOP 0x40000000 196 #define TLAN_HC_ACK 0x20000000 197 #define TLAN_HC_CS_MASK 0x1FE00000 198 #define TLAN_HC_EOC 0x00100000 199 #define TLAN_HC_RT 0x00080000 200 #define TLAN_HC_NES 0x00040000 201 #define TLAN_HC_AD_RST 0x00008000 202 #define TLAN_HC_LD_TMR 0x00004000 203 #define TLAN_HC_LD_THR 0x00002000 204 #define TLAN_HC_REQ_INT 0x00001000 205 #define TLAN_HC_INT_OFF 0x00000800 206 #define TLAN_HC_INT_ON 0x00000400 207 #define TLAN_HC_AC_MASK 0x000000FF 208 #define TLAN_CH_PARM 0x04 209 #define TLAN_DIO_ADR 0x08 210 #define TLAN_DA_ADR_INC 0x8000 211 #define TLAN_DA_RAM_ADR 0x4000 212 #define TLAN_HOST_INT 0x0A 213 #define TLAN_HI_IV_MASK 0x1FE0 214 #define TLAN_HI_IT_MASK 0x001C 215 #define TLAN_DIO_DATA 0x0C 216 217 218 /* ThunderLAN Internal Register DIO Offsets */ 219 220 #define TLAN_NET_CMD 0x00 221 #define TLAN_NET_CMD_NRESET 0x80 222 #define TLAN_NET_CMD_NWRAP 0x40 223 #define TLAN_NET_CMD_CSF 0x20 224 #define TLAN_NET_CMD_CAF 0x10 225 #define TLAN_NET_CMD_NOBRX 0x08 226 #define TLAN_NET_CMD_DUPLEX 0x04 227 #define TLAN_NET_CMD_TRFRAM 0x02 228 #define TLAN_NET_CMD_TXPACE 0x01 229 #define TLAN_NET_SIO 0x01 230 #define TLAN_NET_SIO_MINTEN 0x80 231 #define TLAN_NET_SIO_ECLOK 0x40 232 #define TLAN_NET_SIO_ETXEN 0x20 233 #define TLAN_NET_SIO_EDATA 0x10 234 #define TLAN_NET_SIO_NMRST 0x08 235 #define TLAN_NET_SIO_MCLK 0x04 236 #define TLAN_NET_SIO_MTXEN 0x02 237 #define TLAN_NET_SIO_MDATA 0x01 238 #define TLAN_NET_STS 0x02 239 #define TLAN_NET_STS_MIRQ 0x80 240 #define TLAN_NET_STS_HBEAT 0x40 241 #define TLAN_NET_STS_TXSTOP 0x20 242 #define TLAN_NET_STS_RXSTOP 0x10 243 #define TLAN_NET_STS_RSRVD 0x0F 244 #define TLAN_NET_MASK 0x03 245 #define TLAN_NET_MASK_MASK7 0x80 246 #define TLAN_NET_MASK_MASK6 0x40 247 #define TLAN_NET_MASK_MASK5 0x20 248 #define TLAN_NET_MASK_MASK4 0x10 249 #define TLAN_NET_MASK_RSRVD 0x0F 250 #define TLAN_NET_CONFIG 0x04 251 #define TLAN_NET_CFG_RCLK 0x8000 252 #define TLAN_NET_CFG_TCLK 0x4000 253 #define TLAN_NET_CFG_BIT 0x2000 254 #define TLAN_NET_CFG_RXCRC 0x1000 255 #define TLAN_NET_CFG_PEF 0x0800 256 #define TLAN_NET_CFG_1FRAG 0x0400 257 #define TLAN_NET_CFG_1CHAN 0x0200 258 #define TLAN_NET_CFG_MTEST 0x0100 259 #define TLAN_NET_CFG_PHY_EN 0x0080 260 #define TLAN_NET_CFG_MSMASK 0x007F 261 #define TLAN_MAN_TEST 0x06 262 #define TLAN_DEF_VENDOR_ID 0x08 263 #define TLAN_DEF_DEVICE_ID 0x0A 264 #define TLAN_DEF_REVISION 0x0C 265 #define TLAN_DEF_SUBCLASS 0x0D 266 #define TLAN_DEF_MIN_LAT 0x0E 267 #define TLAN_DEF_MAX_LAT 0x0F 268 #define TLAN_AREG_0 0x10 269 #define TLAN_AREG_1 0x16 270 #define TLAN_AREG_2 0x1C 271 #define TLAN_AREG_3 0x22 272 #define TLAN_HASH_1 0x28 273 #define TLAN_HASH_2 0x2C 274 #define TLAN_GOOD_TX_FRMS 0x30 275 #define TLAN_TX_UNDERUNS 0x33 276 #define TLAN_GOOD_RX_FRMS 0x34 277 #define TLAN_RX_OVERRUNS 0x37 278 #define TLAN_DEFERRED_TX 0x38 279 #define TLAN_CRC_ERRORS 0x3A 280 #define TLAN_CODE_ERRORS 0x3B 281 #define TLAN_MULTICOL_FRMS 0x3C 282 #define TLAN_SINGLECOL_FRMS 0x3E 283 #define TLAN_EXCESSCOL_FRMS 0x40 284 #define TLAN_LATE_COLS 0x41 285 #define TLAN_CARRIER_LOSS 0x42 286 #define TLAN_ACOMMIT 0x43 287 #define TLAN_LED_REG 0x44 288 #define TLAN_LED_ACT 0x10 289 #define TLAN_LED_LINK 0x01 290 #define TLAN_BSIZE_REG 0x45 291 #define TLAN_MAX_RX 0x46 292 #define TLAN_INT_DIS 0x48 293 #define TLAN_ID_TX_EOC 0x04 294 #define TLAN_ID_RX_EOF 0x02 295 #define TLAN_ID_RX_EOC 0x01 296 297 298 299 /* ThunderLAN Interrupt Codes */ 300 301 #define TLAN_INT_NUMBER_OF_INTS 8 302 303 #define TLAN_INT_NONE 0x0000 304 #define TLAN_INT_TX_EOF 0x0001 305 #define TLAN_INT_STAT_OVERFLOW 0x0002 306 #define TLAN_INT_RX_EOF 0x0003 307 #define TLAN_INT_DUMMY 0x0004 308 #define TLAN_INT_TX_EOC 0x0005 309 #define TLAN_INT_STATUS_CHECK 0x0006 310 #define TLAN_INT_RX_EOC 0x0007 311 312 313 314 /* ThunderLAN MII Registers */ 315 316 /* ThunderLAN Specific MII/PHY Registers */ 317 318 #define TLAN_TLPHY_ID 0x10 319 #define TLAN_TLPHY_CTL 0x11 320 #define TLAN_TC_IGLINK 0x8000 321 #define TLAN_TC_SWAPOL 0x4000 322 #define TLAN_TC_AUISEL 0x2000 323 #define TLAN_TC_SQEEN 0x1000 324 #define TLAN_TC_MTEST 0x0800 325 #define TLAN_TC_RESERVED 0x07F8 326 #define TLAN_TC_NFEW 0x0004 327 #define TLAN_TC_INTEN 0x0002 328 #define TLAN_TC_TINT 0x0001 329 #define TLAN_TLPHY_STS 0x12 330 #define TLAN_TS_MINT 0x8000 331 #define TLAN_TS_PHOK 0x4000 332 #define TLAN_TS_POLOK 0x2000 333 #define TLAN_TS_TPENERGY 0x1000 334 #define TLAN_TS_RESERVED 0x0FFF 335 #define TLAN_TLPHY_PAR 0x19 336 #define TLAN_PHY_CIM_STAT 0x0020 337 #define TLAN_PHY_SPEED_100 0x0040 338 #define TLAN_PHY_DUPLEX_FULL 0x0080 339 #define TLAN_PHY_AN_EN_STAT 0x0400 340 341 /* National Sem. & Level1 PHY id's */ 342 #define NAT_SEM_ID1 0x2000 343 #define NAT_SEM_ID2 0x5C01 344 #define LEVEL1_ID1 0x7810 345 #define LEVEL1_ID2 0x0000 346 347 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0 348 349 /* Routines to access internal registers. */ 350 351 static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr) 352 { 353 outw(internal_addr, base_addr + TLAN_DIO_ADR); 354 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3))); 355 356 } /* TLan_DioRead8 */ 357 358 359 360 361 static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr) 362 { 363 outw(internal_addr, base_addr + TLAN_DIO_ADR); 364 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2))); 365 366 } /* TLan_DioRead16 */ 367 368 369 370 371 static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr) 372 { 373 outw(internal_addr, base_addr + TLAN_DIO_ADR); 374 return (inl(base_addr + TLAN_DIO_DATA)); 375 376 } /* TLan_DioRead32 */ 377 378 379 380 381 static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data) 382 { 383 outw(internal_addr, base_addr + TLAN_DIO_ADR); 384 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); 385 386 } 387 388 389 390 391 static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data) 392 { 393 outw(internal_addr, base_addr + TLAN_DIO_ADR); 394 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); 395 396 } 397 398 399 400 401 static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data) 402 { 403 outw(internal_addr, base_addr + TLAN_DIO_ADR); 404 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); 405 406 } 407 408 409 410 #if 0 411 static inline void TLan_ClearBit(u8 bit, u16 port) 412 { 413 outb_p(inb_p(port) & ~bit, port); 414 } 415 416 417 418 419 static inline int TLan_GetBit(u8 bit, u16 port) 420 { 421 return ((int) (inb_p(port) & bit)); 422 } 423 424 425 426 427 static inline void TLan_SetBit(u8 bit, u16 port) 428 { 429 outb_p(inb_p(port) | bit, port); 430 } 431 #endif 432 433 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port) 434 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit)) 435 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port) 436 437 #ifdef I_LIKE_A_FAST_HASH_FUNCTION 438 /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */ 439 /* the code below is about seven times as fast as the original code */ 440 static inline u32 TLan_HashFunc(u8 * a) 441 { 442 u8 hash; 443 444 hash = (a[0] ^ a[3]); /* & 077 */ 445 hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */ 446 hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */ 447 hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */ 448 hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */ 449 hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */ 450 451 return (hash & 077); 452 } 453 454 #else /* original code */ 455 456 static inline u32 xor(u32 a, u32 b) 457 { 458 return ((a && !b) || (!a && b)); 459 } 460 461 #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) 462 #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) 463 464 static inline u32 TLan_HashFunc(u8 * a) 465 { 466 u32 hash; 467 468 hash = 469 XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24), 470 DA(a, 30), DA(a, 36), DA(a, 42)); 471 hash |= 472 XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25), 473 DA(a, 31), DA(a, 37), DA(a, 43)) << 1; 474 hash |= 475 XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26), 476 DA(a, 32), DA(a, 38), DA(a, 44)) << 2; 477 hash |= 478 XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27), 479 DA(a, 33), DA(a, 39), DA(a, 45)) << 3; 480 hash |= 481 XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28), 482 DA(a, 34), DA(a, 40), DA(a, 46)) << 4; 483 hash |= 484 XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29), 485 DA(a, 35), DA(a, 41), DA(a, 47)) << 5; 486 487 return hash; 488 489 } 490 491 #endif /* I_LIKE_A_FAST_HASH_FUNCTION */ 492
