1 /** @file 2 * 3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __PL011_UART_H__ 16 #define __PL011_UART_H__ 17 18 #include <Uefi.h> 19 #include <Protocol/SerialIo.h> 20 21 // PL011 Registers 22 #define UARTDR 0x000 23 #define UARTRSR 0x004 24 #define UARTECR 0x004 25 #define UARTFR 0x018 26 #define UARTILPR 0x020 27 #define UARTIBRD 0x024 28 #define UARTFBRD 0x028 29 #define UARTLCR_H 0x02C 30 #define UARTCR 0x030 31 #define UARTIFLS 0x034 32 #define UARTIMSC 0x038 33 #define UARTRIS 0x03C 34 #define UARTMIS 0x040 35 #define UARTICR 0x044 36 #define UARTDMACR 0x048 37 38 #define UARTPID0 0xFE0 39 #define UARTPID1 0xFE4 40 #define UARTPID2 0xFE8 41 #define UARTPID3 0xFEC 42 43 // Data status bits 44 #define UART_DATA_ERROR_MASK 0x0F00 45 46 // Status reg bits 47 #define UART_STATUS_ERROR_MASK 0x0F 48 49 // Flag reg bits 50 #define PL011_UARTFR_RI (1 << 8) // Ring indicator 51 #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty 52 #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full 53 #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full 54 #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty 55 #define PL011_UARTFR_BUSY (1 << 3) // UART busy 56 #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect 57 #define PL011_UARTFR_DSR (1 << 1) // Data set ready 58 #define PL011_UARTFR_CTS (1 << 0) // Clear to send 59 60 // Flag reg bits - alternative names 61 #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE 62 #define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF 63 #define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF 64 #define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE 65 #define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY 66 67 // Control reg bits 68 #define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable 69 #define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable 70 #define PL011_UARTCR_RTS (1 << 11) // Request to send 71 #define PL011_UARTCR_DTR (1 << 10) // Data transmit ready. 72 #define PL011_UARTCR_RXE (1 << 9) // Receive enable 73 #define PL011_UARTCR_TXE (1 << 8) // Transmit enable 74 #define PL011_UARTCR_LBE (1 << 7) // Loopback enable 75 #define PL011_UARTCR_UARTEN (1 << 0) // UART Enable 76 77 // Line Control Register Bits 78 #define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select 79 #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 80 #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 81 #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 82 #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 83 #define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable 84 #define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select 85 #define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select 86 #define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable 87 #define PL011_UARTLCR_H_BRK (1 << 0) // Send break 88 89 #define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF) 90 #define PL011_VER_R1P4 0x2 91 92 /* 93 94 Programmed hardware of Serial port. 95 96 @return Always return EFI_UNSUPPORTED. 97 98 **/ 99 RETURN_STATUS 100 EFIAPI 101 PL011UartInitializePort ( 102 IN OUT UINTN UartBase, 103 IN OUT UINT64 *BaudRate, 104 IN OUT UINT32 *ReceiveFifoDepth, 105 IN OUT EFI_PARITY_TYPE *Parity, 106 IN OUT UINT8 *DataBits, 107 IN OUT EFI_STOP_BITS_TYPE *StopBits 108 ); 109 110 /** 111 112 Assert or deassert the control signals on a serial port. 113 The following control signals are set according their bit settings : 114 . Request to Send 115 . Data Terminal Ready 116 117 @param[in] UartBase UART registers base address 118 @param[in] Control The following bits are taken into account : 119 . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the 120 "Request To Send" control signal if this bit is 121 equal to one/zero. 122 . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert 123 the "Data Terminal Ready" control signal if this 124 bit is equal to one/zero. 125 . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable 126 the hardware loopback if this bit is equal to 127 one/zero. 128 . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported. 129 . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/ 130 disable the hardware flow control based on CTS (Clear 131 To Send) and RTS (Ready To Send) control signals. 132 133 @retval RETURN_SUCCESS The new control bits were set on the serial device. 134 @retval RETURN_UNSUPPORTED The serial device does not support this operation. 135 136 **/ 137 RETURN_STATUS 138 EFIAPI 139 PL011UartSetControl ( 140 IN UINTN UartBase, 141 IN UINT32 Control 142 ); 143 144 /** 145 146 Retrieve the status of the control bits on a serial device. 147 148 @param[in] UartBase UART registers base address 149 @param[out] Control Status of the control bits on a serial device : 150 151 . EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY, 152 EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT, 153 EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY 154 are all related to the DTE (Data Terminal Equipment) and 155 DCE (Data Communication Equipment) modes of operation of 156 the serial device. 157 . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive 158 buffer is empty, 0 otherwise. 159 . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit 160 buffer is empty, 0 otherwise. 161 . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the 162 hardware loopback is enabled (the ouput feeds the receive 163 buffer), 0 otherwise. 164 . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a 165 loopback is accomplished by software, 0 otherwise. 166 . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the 167 hardware flow control based on CTS (Clear To Send) and RTS 168 (Ready To Send) control signals is enabled, 0 otherwise. 169 170 171 @retval RETURN_SUCCESS The control bits were read from the serial device. 172 173 **/ 174 RETURN_STATUS 175 EFIAPI 176 PL011UartGetControl ( 177 IN UINTN UartBase, 178 OUT UINT32 *Control 179 ); 180 181 /** 182 Write data to serial device. 183 184 @param Buffer Point of data buffer which need to be written. 185 @param NumberOfBytes Number of output bytes which are cached in Buffer. 186 187 @retval 0 Write data failed. 188 @retval !0 Actual number of bytes written to serial device. 189 190 **/ 191 UINTN 192 EFIAPI 193 PL011UartWrite ( 194 IN UINTN UartBase, 195 IN UINT8 *Buffer, 196 IN UINTN NumberOfBytes 197 ); 198 199 /** 200 Read data from serial device and save the data in buffer. 201 202 @param Buffer Point of data buffer which need to be written. 203 @param NumberOfBytes Number of output bytes which are cached in Buffer. 204 205 @retval 0 Read data failed. 206 @retval !0 Actual number of bytes read from serial device. 207 208 **/ 209 UINTN 210 EFIAPI 211 PL011UartRead ( 212 IN UINTN UartBase, 213 OUT UINT8 *Buffer, 214 IN UINTN NumberOfBytes 215 ); 216 217 /** 218 Check to see if any data is available to be read from the debug device. 219 220 @retval EFI_SUCCESS At least one byte of data is available to be read 221 @retval EFI_NOT_READY No data is available to be read 222 @retval EFI_DEVICE_ERROR The serial device is not functioning properly 223 224 **/ 225 BOOLEAN 226 EFIAPI 227 PL011UartPoll ( 228 IN UINTN UartBase 229 ); 230 231 #endif 232
