1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright (C) 1988-2014 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* 80386 instruction printer by Pace Willisson (pace (at) prep.ai.mit.edu) 23 July 1988 24 modified by John Hassey (hassey (at) dg-rtp.dg.com) 25 x86-64 support added by Jan Hubicka (jh (at) suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz). */ 27 28 /* The main tables describing the instructions is essentially a copy 29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 30 Programmers Manual. Usually, there is a capital letter, followed 31 by a small letter. The capital letter tell the addressing mode, 32 and the small letter tells about the operand size. Refer to 33 the Intel manual for details. */ 34 35 #include "sysdep.h" 36 #include "dis-asm.h" 37 #include "opintl.h" 38 #include "opcode/i386.h" 39 #include "libiberty.h" 40 41 #include <setjmp.h> 42 43 static int print_insn (bfd_vma, disassemble_info *); 44 static void dofloat (int); 45 static void OP_ST (int, int); 46 static void OP_STi (int, int); 47 static int putop (const char *, int); 48 static void oappend (const char *); 49 static void append_seg (void); 50 static void OP_indirE (int, int); 51 static void print_operand_value (char *, int, bfd_vma); 52 static void OP_E_register (int, int); 53 static void OP_E_memory (int, int); 54 static void print_displacement (char *, bfd_vma); 55 static void OP_E (int, int); 56 static void OP_G (int, int); 57 static bfd_vma get64 (void); 58 static bfd_signed_vma get32 (void); 59 static bfd_signed_vma get32s (void); 60 static int get16 (void); 61 static void set_op (bfd_vma, int); 62 static void OP_Skip_MODRM (int, int); 63 static void OP_REG (int, int); 64 static void OP_IMREG (int, int); 65 static void OP_I (int, int); 66 static void OP_I64 (int, int); 67 static void OP_sI (int, int); 68 static void OP_J (int, int); 69 static void OP_SEG (int, int); 70 static void OP_DIR (int, int); 71 static void OP_OFF (int, int); 72 static void OP_OFF64 (int, int); 73 static void ptr_reg (int, int); 74 static void OP_ESreg (int, int); 75 static void OP_DSreg (int, int); 76 static void OP_C (int, int); 77 static void OP_D (int, int); 78 static void OP_T (int, int); 79 static void OP_R (int, int); 80 static void OP_MMX (int, int); 81 static void OP_XMM (int, int); 82 static void OP_EM (int, int); 83 static void OP_EX (int, int); 84 static void OP_EMC (int,int); 85 static void OP_MXC (int,int); 86 static void OP_MS (int, int); 87 static void OP_XS (int, int); 88 static void OP_M (int, int); 89 static void OP_VEX (int, int); 90 static void OP_EX_Vex (int, int); 91 static void OP_EX_VexW (int, int); 92 static void OP_EX_VexImmW (int, int); 93 static void OP_XMM_Vex (int, int); 94 static void OP_XMM_VexW (int, int); 95 static void OP_Rounding (int, int); 96 static void OP_REG_VexI4 (int, int); 97 static void PCLMUL_Fixup (int, int); 98 static void VEXI4_Fixup (int, int); 99 static void VZERO_Fixup (int, int); 100 static void VCMP_Fixup (int, int); 101 static void VPCMP_Fixup (int, int); 102 static void OP_0f07 (int, int); 103 static void OP_Monitor (int, int); 104 static void OP_Mwait (int, int); 105 static void NOP_Fixup1 (int, int); 106 static void NOP_Fixup2 (int, int); 107 static void OP_3DNowSuffix (int, int); 108 static void CMP_Fixup (int, int); 109 static void BadOp (void); 110 static void REP_Fixup (int, int); 111 static void BND_Fixup (int, int); 112 static void HLE_Fixup1 (int, int); 113 static void HLE_Fixup2 (int, int); 114 static void HLE_Fixup3 (int, int); 115 static void CMPXCHG8B_Fixup (int, int); 116 static void XMM_Fixup (int, int); 117 static void CRC32_Fixup (int, int); 118 static void FXSAVE_Fixup (int, int); 119 static void OP_LWPCB_E (int, int); 120 static void OP_LWP_E (int, int); 121 static void OP_Vex_2src_1 (int, int); 122 static void OP_Vex_2src_2 (int, int); 123 124 static void MOVBE_Fixup (int, int); 125 126 static void OP_Mask (int, int); 127 128 struct dis_private { 129 /* Points to first byte not fetched. */ 130 bfd_byte *max_fetched; 131 bfd_byte the_buffer[MAX_MNEM_SIZE]; 132 bfd_vma insn_start; 133 int orig_sizeflag; 134 OPCODES_SIGJMP_BUF bailout; 135 }; 136 137 enum address_mode 138 { 139 mode_16bit, 140 mode_32bit, 141 mode_64bit 142 }; 143 144 enum address_mode address_mode; 145 146 /* Flags for the prefixes for the current instruction. See below. */ 147 static int prefixes; 148 149 /* REX prefix the current instruction. See below. */ 150 static int rex; 151 /* Bits of REX we've already used. */ 152 static int rex_used; 153 /* REX bits in original REX prefix ignored. */ 154 static int rex_ignored; 155 /* Mark parts used in the REX prefix. When we are testing for 156 empty prefix (for 8bit register REX extension), just mask it 157 out. Otherwise test for REX bit is excuse for existence of REX 158 only in case value is nonzero. */ 159 #define USED_REX(value) \ 160 { \ 161 if (value) \ 162 { \ 163 if ((rex & value)) \ 164 rex_used |= (value) | REX_OPCODE; \ 165 } \ 166 else \ 167 rex_used |= REX_OPCODE; \ 168 } 169 170 /* Flags for prefixes which we somehow handled when printing the 171 current instruction. */ 172 static int used_prefixes; 173 174 /* Flags stored in PREFIXES. */ 175 #define PREFIX_REPZ 1 176 #define PREFIX_REPNZ 2 177 #define PREFIX_LOCK 4 178 #define PREFIX_CS 8 179 #define PREFIX_SS 0x10 180 #define PREFIX_DS 0x20 181 #define PREFIX_ES 0x40 182 #define PREFIX_FS 0x80 183 #define PREFIX_GS 0x100 184 #define PREFIX_DATA 0x200 185 #define PREFIX_ADDR 0x400 186 #define PREFIX_FWAIT 0x800 187 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps 190 on error. */ 191 #define FETCH_DATA(info, addr) \ 192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ 193 ? 1 : fetch_data ((info), (addr))) 194 195 static int 196 fetch_data (struct disassemble_info *info, bfd_byte *addr) 197 { 198 int status; 199 struct dis_private *priv = (struct dis_private *) info->private_data; 200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 201 202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE) 203 status = (*info->read_memory_func) (start, 204 priv->max_fetched, 205 addr - priv->max_fetched, 206 info); 207 else 208 status = -1; 209 if (status != 0) 210 { 211 /* If we did manage to read at least one byte, then 212 print_insn_i386 will do something sensible. Otherwise, print 213 an error. We do that here because this is where we know 214 STATUS. */ 215 if (priv->max_fetched == priv->the_buffer) 216 (*info->memory_error_func) (status, start, info); 217 OPCODES_SIGLONGJMP (priv->bailout, 1); 218 } 219 else 220 priv->max_fetched = addr; 221 return 1; 222 } 223 224 #define XX { NULL, 0 } 225 #define Bad_Opcode NULL, { { NULL, 0 } } 226 227 #define Eb { OP_E, b_mode } 228 #define Ebnd { OP_E, bnd_mode } 229 #define EbS { OP_E, b_swap_mode } 230 #define Ev { OP_E, v_mode } 231 #define Ev_bnd { OP_E, v_bnd_mode } 232 #define EvS { OP_E, v_swap_mode } 233 #define Ed { OP_E, d_mode } 234 #define Edq { OP_E, dq_mode } 235 #define Edqw { OP_E, dqw_mode } 236 #define EdqwS { OP_E, dqw_swap_mode } 237 #define Edqb { OP_E, dqb_mode } 238 #define Edb { OP_E, db_mode } 239 #define Edw { OP_E, dw_mode } 240 #define Edqd { OP_E, dqd_mode } 241 #define Eq { OP_E, q_mode } 242 #define indirEv { OP_indirE, stack_v_mode } 243 #define indirEp { OP_indirE, f_mode } 244 #define stackEv { OP_E, stack_v_mode } 245 #define Em { OP_E, m_mode } 246 #define Ew { OP_E, w_mode } 247 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 248 #define Ma { OP_M, a_mode } 249 #define Mb { OP_M, b_mode } 250 #define Md { OP_M, d_mode } 251 #define Mo { OP_M, o_mode } 252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 253 #define Mq { OP_M, q_mode } 254 #define Mx { OP_M, x_mode } 255 #define Mxmm { OP_M, xmm_mode } 256 #define Gb { OP_G, b_mode } 257 #define Gbnd { OP_G, bnd_mode } 258 #define Gv { OP_G, v_mode } 259 #define Gd { OP_G, d_mode } 260 #define Gdq { OP_G, dq_mode } 261 #define Gm { OP_G, m_mode } 262 #define Gw { OP_G, w_mode } 263 #define Rd { OP_R, d_mode } 264 #define Rdq { OP_R, dq_mode } 265 #define Rm { OP_R, m_mode } 266 #define Ib { OP_I, b_mode } 267 #define sIb { OP_sI, b_mode } /* sign extened byte */ 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ 269 #define Iv { OP_I, v_mode } 270 #define sIv { OP_sI, v_mode } 271 #define Iq { OP_I, q_mode } 272 #define Iv64 { OP_I64, v_mode } 273 #define Iw { OP_I, w_mode } 274 #define I1 { OP_I, const_1_mode } 275 #define Jb { OP_J, b_mode } 276 #define Jv { OP_J, v_mode } 277 #define Cm { OP_C, m_mode } 278 #define Dm { OP_D, m_mode } 279 #define Td { OP_T, d_mode } 280 #define Skip_MODRM { OP_Skip_MODRM, 0 } 281 282 #define RMeAX { OP_REG, eAX_reg } 283 #define RMeBX { OP_REG, eBX_reg } 284 #define RMeCX { OP_REG, eCX_reg } 285 #define RMeDX { OP_REG, eDX_reg } 286 #define RMeSP { OP_REG, eSP_reg } 287 #define RMeBP { OP_REG, eBP_reg } 288 #define RMeSI { OP_REG, eSI_reg } 289 #define RMeDI { OP_REG, eDI_reg } 290 #define RMrAX { OP_REG, rAX_reg } 291 #define RMrBX { OP_REG, rBX_reg } 292 #define RMrCX { OP_REG, rCX_reg } 293 #define RMrDX { OP_REG, rDX_reg } 294 #define RMrSP { OP_REG, rSP_reg } 295 #define RMrBP { OP_REG, rBP_reg } 296 #define RMrSI { OP_REG, rSI_reg } 297 #define RMrDI { OP_REG, rDI_reg } 298 #define RMAL { OP_REG, al_reg } 299 #define RMCL { OP_REG, cl_reg } 300 #define RMDL { OP_REG, dl_reg } 301 #define RMBL { OP_REG, bl_reg } 302 #define RMAH { OP_REG, ah_reg } 303 #define RMCH { OP_REG, ch_reg } 304 #define RMDH { OP_REG, dh_reg } 305 #define RMBH { OP_REG, bh_reg } 306 #define RMAX { OP_REG, ax_reg } 307 #define RMDX { OP_REG, dx_reg } 308 309 #define eAX { OP_IMREG, eAX_reg } 310 #define eBX { OP_IMREG, eBX_reg } 311 #define eCX { OP_IMREG, eCX_reg } 312 #define eDX { OP_IMREG, eDX_reg } 313 #define eSP { OP_IMREG, eSP_reg } 314 #define eBP { OP_IMREG, eBP_reg } 315 #define eSI { OP_IMREG, eSI_reg } 316 #define eDI { OP_IMREG, eDI_reg } 317 #define AL { OP_IMREG, al_reg } 318 #define CL { OP_IMREG, cl_reg } 319 #define DL { OP_IMREG, dl_reg } 320 #define BL { OP_IMREG, bl_reg } 321 #define AH { OP_IMREG, ah_reg } 322 #define CH { OP_IMREG, ch_reg } 323 #define DH { OP_IMREG, dh_reg } 324 #define BH { OP_IMREG, bh_reg } 325 #define AX { OP_IMREG, ax_reg } 326 #define DX { OP_IMREG, dx_reg } 327 #define zAX { OP_IMREG, z_mode_ax_reg } 328 #define indirDX { OP_IMREG, indir_dx_reg } 329 330 #define Sw { OP_SEG, w_mode } 331 #define Sv { OP_SEG, v_mode } 332 #define Ap { OP_DIR, 0 } 333 #define Ob { OP_OFF64, b_mode } 334 #define Ov { OP_OFF64, v_mode } 335 #define Xb { OP_DSreg, eSI_reg } 336 #define Xv { OP_DSreg, eSI_reg } 337 #define Xz { OP_DSreg, eSI_reg } 338 #define Yb { OP_ESreg, eDI_reg } 339 #define Yv { OP_ESreg, eDI_reg } 340 #define DSBX { OP_DSreg, eBX_reg } 341 342 #define es { OP_REG, es_reg } 343 #define ss { OP_REG, ss_reg } 344 #define cs { OP_REG, cs_reg } 345 #define ds { OP_REG, ds_reg } 346 #define fs { OP_REG, fs_reg } 347 #define gs { OP_REG, gs_reg } 348 349 #define MX { OP_MMX, 0 } 350 #define XM { OP_XMM, 0 } 351 #define XMScalar { OP_XMM, scalar_mode } 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } 353 #define XMM { OP_XMM, xmm_mode } 354 #define XMxmmq { OP_XMM, xmmq_mode } 355 #define EM { OP_EM, v_mode } 356 #define EMS { OP_EM, v_swap_mode } 357 #define EMd { OP_EM, d_mode } 358 #define EMx { OP_EM, x_mode } 359 #define EXw { OP_EX, w_mode } 360 #define EXd { OP_EX, d_mode } 361 #define EXdScalar { OP_EX, d_scalar_mode } 362 #define EXdS { OP_EX, d_swap_mode } 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode } 364 #define EXq { OP_EX, q_mode } 365 #define EXqScalar { OP_EX, q_scalar_mode } 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode } 367 #define EXqS { OP_EX, q_swap_mode } 368 #define EXx { OP_EX, x_mode } 369 #define EXxS { OP_EX, x_swap_mode } 370 #define EXxmm { OP_EX, xmm_mode } 371 #define EXymm { OP_EX, ymm_mode } 372 #define EXxmmq { OP_EX, xmmq_mode } 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } 374 #define EXxmm_mb { OP_EX, xmm_mb_mode } 375 #define EXxmm_mw { OP_EX, xmm_mw_mode } 376 #define EXxmm_md { OP_EX, xmm_md_mode } 377 #define EXxmm_mq { OP_EX, xmm_mq_mode } 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode } 379 #define EXxmmdw { OP_EX, xmmdw_mode } 380 #define EXxmmqd { OP_EX, xmmqd_mode } 381 #define EXymmq { OP_EX, ymmq_mode } 382 #define EXVexWdq { OP_EX, vex_w_dq_mode } 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } 386 #define MS { OP_MS, v_mode } 387 #define XS { OP_XS, v_mode } 388 #define EMCq { OP_EMC, q_mode } 389 #define MXC { OP_MXC, 0 } 390 #define OPSUF { OP_3DNowSuffix, 0 } 391 #define CMP { CMP_Fixup, 0 } 392 #define XMM0 { XMM_Fixup, 0 } 393 #define FXSAVE { FXSAVE_Fixup, 0 } 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 } 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 } 396 397 #define Vex { OP_VEX, vex_mode } 398 #define VexScalar { OP_VEX, vex_scalar_mode } 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } 400 #define Vex128 { OP_VEX, vex128_mode } 401 #define Vex256 { OP_VEX, vex256_mode } 402 #define VexGdq { OP_VEX, dq_mode } 403 #define VexI4 { VEXI4_Fixup, 0} 404 #define EXdVex { OP_EX_Vex, d_mode } 405 #define EXdVexS { OP_EX_Vex, d_swap_mode } 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } 407 #define EXqVex { OP_EX_Vex, q_mode } 408 #define EXqVexS { OP_EX_Vex, q_swap_mode } 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } 410 #define EXVexW { OP_EX_VexW, x_mode } 411 #define EXdVexW { OP_EX_VexW, d_mode } 412 #define EXqVexW { OP_EX_VexW, q_mode } 413 #define EXVexImmW { OP_EX_VexImmW, x_mode } 414 #define XMVex { OP_XMM_Vex, 0 } 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode } 416 #define XMVexW { OP_XMM_VexW, 0 } 417 #define XMVexI4 { OP_REG_VexI4, x_mode } 418 #define PCLMUL { PCLMUL_Fixup, 0 } 419 #define VZERO { VZERO_Fixup, 0 } 420 #define VCMP { VCMP_Fixup, 0 } 421 #define VPCMP { VPCMP_Fixup, 0 } 422 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode } 424 #define EXxEVexS { OP_Rounding, evex_sae_mode } 425 426 #define XMask { OP_Mask, mask_mode } 427 #define MaskG { OP_G, mask_mode } 428 #define MaskE { OP_E, mask_mode } 429 #define MaskBDE { OP_E, mask_bd_mode } 430 #define MaskR { OP_R, mask_mode } 431 #define MaskVex { OP_VEX, mask_mode } 432 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } 437 438 /* Used handle "rep" prefix for string instructions. */ 439 #define Xbr { REP_Fixup, eSI_reg } 440 #define Xvr { REP_Fixup, eSI_reg } 441 #define Ybr { REP_Fixup, eDI_reg } 442 #define Yvr { REP_Fixup, eDI_reg } 443 #define Yzr { REP_Fixup, eDI_reg } 444 #define indirDXr { REP_Fixup, indir_dx_reg } 445 #define ALr { REP_Fixup, al_reg } 446 #define eAXr { REP_Fixup, eAX_reg } 447 448 /* Used handle HLE prefix for lockable instructions. */ 449 #define Ebh1 { HLE_Fixup1, b_mode } 450 #define Evh1 { HLE_Fixup1, v_mode } 451 #define Ebh2 { HLE_Fixup2, b_mode } 452 #define Evh2 { HLE_Fixup2, v_mode } 453 #define Ebh3 { HLE_Fixup3, b_mode } 454 #define Evh3 { HLE_Fixup3, v_mode } 455 456 #define BND { BND_Fixup, 0 } 457 458 #define cond_jump_flag { NULL, cond_jump_mode } 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 460 461 /* bits in sizeflag */ 462 #define SUFFIX_ALWAYS 4 463 #define AFLAG 2 464 #define DFLAG 1 465 466 enum 467 { 468 /* byte operand */ 469 b_mode = 1, 470 /* byte operand with operand swapped */ 471 b_swap_mode, 472 /* byte operand, sign extend like 'T' suffix */ 473 b_T_mode, 474 /* operand size depends on prefixes */ 475 v_mode, 476 /* operand size depends on prefixes with operand swapped */ 477 v_swap_mode, 478 /* word operand */ 479 w_mode, 480 /* double word operand */ 481 d_mode, 482 /* double word operand with operand swapped */ 483 d_swap_mode, 484 /* quad word operand */ 485 q_mode, 486 /* quad word operand with operand swapped */ 487 q_swap_mode, 488 /* ten-byte operand */ 489 t_mode, 490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with 491 broadcast enabled. */ 492 x_mode, 493 /* Similar to x_mode, but with different EVEX mem shifts. */ 494 evex_x_gscat_mode, 495 /* Similar to x_mode, but with disabled broadcast. */ 496 evex_x_nobcst_mode, 497 /* Similar to x_mode, but with operands swapped and disabled broadcast 498 in EVEX. */ 499 x_swap_mode, 500 /* 16-byte XMM operand */ 501 xmm_mode, 502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword 503 memory operand (depending on vector length). Broadcast isn't 504 allowed. */ 505 xmmq_mode, 506 /* Same as xmmq_mode, but broadcast is allowed. */ 507 evex_half_bcst_xmmq_mode, 508 /* XMM register or byte memory operand */ 509 xmm_mb_mode, 510 /* XMM register or word memory operand */ 511 xmm_mw_mode, 512 /* XMM register or double word memory operand */ 513 xmm_md_mode, 514 /* XMM register or quad word memory operand */ 515 xmm_mq_mode, 516 /* XMM register or double/quad word memory operand, depending on 517 VEX.W. */ 518 xmm_mdq_mode, 519 /* 16-byte XMM, word, double word or quad word operand. */ 520 xmmdw_mode, 521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */ 522 xmmqd_mode, 523 /* 32-byte YMM operand */ 524 ymm_mode, 525 /* quad word, ymmword or zmmword memory operand. */ 526 ymmq_mode, 527 /* 32-byte YMM or 16-byte word operand */ 528 ymmxmm_mode, 529 /* d_mode in 32bit, q_mode in 64bit mode. */ 530 m_mode, 531 /* pair of v_mode operands */ 532 a_mode, 533 cond_jump_mode, 534 loop_jcxz_mode, 535 v_bnd_mode, 536 /* operand size depends on REX prefixes. */ 537 dq_mode, 538 /* registers like dq_mode, memory like w_mode. */ 539 dqw_mode, 540 dqw_swap_mode, 541 bnd_mode, 542 /* 4- or 6-byte pointer operand */ 543 f_mode, 544 const_1_mode, 545 /* v_mode for stack-related opcodes. */ 546 stack_v_mode, 547 /* non-quad operand size depends on prefixes */ 548 z_mode, 549 /* 16-byte operand */ 550 o_mode, 551 /* registers like dq_mode, memory like b_mode. */ 552 dqb_mode, 553 /* registers like d_mode, memory like b_mode. */ 554 db_mode, 555 /* registers like d_mode, memory like w_mode. */ 556 dw_mode, 557 /* registers like dq_mode, memory like d_mode. */ 558 dqd_mode, 559 /* normal vex mode */ 560 vex_mode, 561 /* 128bit vex mode */ 562 vex128_mode, 563 /* 256bit vex mode */ 564 vex256_mode, 565 /* operand size depends on the VEX.W bit. */ 566 vex_w_dq_mode, 567 568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */ 569 vex_vsib_d_w_dq_mode, 570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ 571 vex_vsib_d_w_d_mode, 572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */ 573 vex_vsib_q_w_dq_mode, 574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ 575 vex_vsib_q_w_d_mode, 576 577 /* scalar, ignore vector length. */ 578 scalar_mode, 579 /* like d_mode, ignore vector length. */ 580 d_scalar_mode, 581 /* like d_swap_mode, ignore vector length. */ 582 d_scalar_swap_mode, 583 /* like q_mode, ignore vector length. */ 584 q_scalar_mode, 585 /* like q_swap_mode, ignore vector length. */ 586 q_scalar_swap_mode, 587 /* like vex_mode, ignore vector length. */ 588 vex_scalar_mode, 589 /* like vex_w_dq_mode, ignore vector length. */ 590 vex_scalar_w_dq_mode, 591 592 /* Static rounding. */ 593 evex_rounding_mode, 594 /* Supress all exceptions. */ 595 evex_sae_mode, 596 597 /* Mask register operand. */ 598 mask_mode, 599 /* Mask register operand. */ 600 mask_bd_mode, 601 602 es_reg, 603 cs_reg, 604 ss_reg, 605 ds_reg, 606 fs_reg, 607 gs_reg, 608 609 eAX_reg, 610 eCX_reg, 611 eDX_reg, 612 eBX_reg, 613 eSP_reg, 614 eBP_reg, 615 eSI_reg, 616 eDI_reg, 617 618 al_reg, 619 cl_reg, 620 dl_reg, 621 bl_reg, 622 ah_reg, 623 ch_reg, 624 dh_reg, 625 bh_reg, 626 627 ax_reg, 628 cx_reg, 629 dx_reg, 630 bx_reg, 631 sp_reg, 632 bp_reg, 633 si_reg, 634 di_reg, 635 636 rAX_reg, 637 rCX_reg, 638 rDX_reg, 639 rBX_reg, 640 rSP_reg, 641 rBP_reg, 642 rSI_reg, 643 rDI_reg, 644 645 z_mode_ax_reg, 646 indir_dx_reg 647 }; 648 649 enum 650 { 651 FLOATCODE = 1, 652 USE_REG_TABLE, 653 USE_MOD_TABLE, 654 USE_RM_TABLE, 655 USE_PREFIX_TABLE, 656 USE_X86_64_TABLE, 657 USE_3BYTE_TABLE, 658 USE_XOP_8F_TABLE, 659 USE_VEX_C4_TABLE, 660 USE_VEX_C5_TABLE, 661 USE_VEX_LEN_TABLE, 662 USE_VEX_W_TABLE, 663 USE_EVEX_TABLE 664 }; 665 666 #define FLOAT NULL, { { NULL, FLOATCODE } } 667 668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } 669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) 676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) 677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) 678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) 680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) 681 682 enum 683 { 684 REG_80 = 0, 685 REG_81, 686 REG_82, 687 REG_8F, 688 REG_C0, 689 REG_C1, 690 REG_C6, 691 REG_C7, 692 REG_D0, 693 REG_D1, 694 REG_D2, 695 REG_D3, 696 REG_F6, 697 REG_F7, 698 REG_FE, 699 REG_FF, 700 REG_0F00, 701 REG_0F01, 702 REG_0F0D, 703 REG_0F18, 704 REG_0F71, 705 REG_0F72, 706 REG_0F73, 707 REG_0FA6, 708 REG_0FA7, 709 REG_0FAE, 710 REG_0FBA, 711 REG_0FC7, 712 REG_VEX_0F71, 713 REG_VEX_0F72, 714 REG_VEX_0F73, 715 REG_VEX_0FAE, 716 REG_VEX_0F38F3, 717 REG_XOP_LWPCB, 718 REG_XOP_LWP, 719 REG_XOP_TBM_01, 720 REG_XOP_TBM_02, 721 722 REG_EVEX_0F71, 723 REG_EVEX_0F72, 724 REG_EVEX_0F73, 725 REG_EVEX_0F38C6, 726 REG_EVEX_0F38C7 727 }; 728 729 enum 730 { 731 MOD_8D = 0, 732 MOD_C6_REG_7, 733 MOD_C7_REG_7, 734 MOD_FF_REG_3, 735 MOD_FF_REG_5, 736 MOD_0F01_REG_0, 737 MOD_0F01_REG_1, 738 MOD_0F01_REG_2, 739 MOD_0F01_REG_3, 740 MOD_0F01_REG_7, 741 MOD_0F12_PREFIX_0, 742 MOD_0F13, 743 MOD_0F16_PREFIX_0, 744 MOD_0F17, 745 MOD_0F18_REG_0, 746 MOD_0F18_REG_1, 747 MOD_0F18_REG_2, 748 MOD_0F18_REG_3, 749 MOD_0F18_REG_4, 750 MOD_0F18_REG_5, 751 MOD_0F18_REG_6, 752 MOD_0F18_REG_7, 753 MOD_0F1A_PREFIX_0, 754 MOD_0F1B_PREFIX_0, 755 MOD_0F1B_PREFIX_1, 756 MOD_0F24, 757 MOD_0F26, 758 MOD_0F2B_PREFIX_0, 759 MOD_0F2B_PREFIX_1, 760 MOD_0F2B_PREFIX_2, 761 MOD_0F2B_PREFIX_3, 762 MOD_0F51, 763 MOD_0F71_REG_2, 764 MOD_0F71_REG_4, 765 MOD_0F71_REG_6, 766 MOD_0F72_REG_2, 767 MOD_0F72_REG_4, 768 MOD_0F72_REG_6, 769 MOD_0F73_REG_2, 770 MOD_0F73_REG_3, 771 MOD_0F73_REG_6, 772 MOD_0F73_REG_7, 773 MOD_0FAE_REG_0, 774 MOD_0FAE_REG_1, 775 MOD_0FAE_REG_2, 776 MOD_0FAE_REG_3, 777 MOD_0FAE_REG_4, 778 MOD_0FAE_REG_5, 779 MOD_0FAE_REG_6, 780 MOD_0FAE_REG_7, 781 MOD_0FB2, 782 MOD_0FB4, 783 MOD_0FB5, 784 MOD_0FC7_REG_3, 785 MOD_0FC7_REG_4, 786 MOD_0FC7_REG_5, 787 MOD_0FC7_REG_6, 788 MOD_0FC7_REG_7, 789 MOD_0FD7, 790 MOD_0FE7_PREFIX_2, 791 MOD_0FF0_PREFIX_3, 792 MOD_0F382A_PREFIX_2, 793 MOD_62_32BIT, 794 MOD_C4_32BIT, 795 MOD_C5_32BIT, 796 MOD_VEX_0F12_PREFIX_0, 797 MOD_VEX_0F13, 798 MOD_VEX_0F16_PREFIX_0, 799 MOD_VEX_0F17, 800 MOD_VEX_0F2B, 801 MOD_VEX_0F50, 802 MOD_VEX_0F71_REG_2, 803 MOD_VEX_0F71_REG_4, 804 MOD_VEX_0F71_REG_6, 805 MOD_VEX_0F72_REG_2, 806 MOD_VEX_0F72_REG_4, 807 MOD_VEX_0F72_REG_6, 808 MOD_VEX_0F73_REG_2, 809 MOD_VEX_0F73_REG_3, 810 MOD_VEX_0F73_REG_6, 811 MOD_VEX_0F73_REG_7, 812 MOD_VEX_0FAE_REG_2, 813 MOD_VEX_0FAE_REG_3, 814 MOD_VEX_0FD7_PREFIX_2, 815 MOD_VEX_0FE7_PREFIX_2, 816 MOD_VEX_0FF0_PREFIX_3, 817 MOD_VEX_0F381A_PREFIX_2, 818 MOD_VEX_0F382A_PREFIX_2, 819 MOD_VEX_0F382C_PREFIX_2, 820 MOD_VEX_0F382D_PREFIX_2, 821 MOD_VEX_0F382E_PREFIX_2, 822 MOD_VEX_0F382F_PREFIX_2, 823 MOD_VEX_0F385A_PREFIX_2, 824 MOD_VEX_0F388C_PREFIX_2, 825 MOD_VEX_0F388E_PREFIX_2, 826 827 MOD_EVEX_0F10_PREFIX_1, 828 MOD_EVEX_0F10_PREFIX_3, 829 MOD_EVEX_0F11_PREFIX_1, 830 MOD_EVEX_0F11_PREFIX_3, 831 MOD_EVEX_0F12_PREFIX_0, 832 MOD_EVEX_0F16_PREFIX_0, 833 MOD_EVEX_0F38C6_REG_1, 834 MOD_EVEX_0F38C6_REG_2, 835 MOD_EVEX_0F38C6_REG_5, 836 MOD_EVEX_0F38C6_REG_6, 837 MOD_EVEX_0F38C7_REG_1, 838 MOD_EVEX_0F38C7_REG_2, 839 MOD_EVEX_0F38C7_REG_5, 840 MOD_EVEX_0F38C7_REG_6 841 }; 842 843 enum 844 { 845 RM_C6_REG_7 = 0, 846 RM_C7_REG_7, 847 RM_0F01_REG_0, 848 RM_0F01_REG_1, 849 RM_0F01_REG_2, 850 RM_0F01_REG_3, 851 RM_0F01_REG_7, 852 RM_0FAE_REG_5, 853 RM_0FAE_REG_6, 854 RM_0FAE_REG_7 855 }; 856 857 enum 858 { 859 PREFIX_90 = 0, 860 PREFIX_0F10, 861 PREFIX_0F11, 862 PREFIX_0F12, 863 PREFIX_0F16, 864 PREFIX_0F1A, 865 PREFIX_0F1B, 866 PREFIX_0F2A, 867 PREFIX_0F2B, 868 PREFIX_0F2C, 869 PREFIX_0F2D, 870 PREFIX_0F2E, 871 PREFIX_0F2F, 872 PREFIX_0F51, 873 PREFIX_0F52, 874 PREFIX_0F53, 875 PREFIX_0F58, 876 PREFIX_0F59, 877 PREFIX_0F5A, 878 PREFIX_0F5B, 879 PREFIX_0F5C, 880 PREFIX_0F5D, 881 PREFIX_0F5E, 882 PREFIX_0F5F, 883 PREFIX_0F60, 884 PREFIX_0F61, 885 PREFIX_0F62, 886 PREFIX_0F6C, 887 PREFIX_0F6D, 888 PREFIX_0F6F, 889 PREFIX_0F70, 890 PREFIX_0F73_REG_3, 891 PREFIX_0F73_REG_7, 892 PREFIX_0F78, 893 PREFIX_0F79, 894 PREFIX_0F7C, 895 PREFIX_0F7D, 896 PREFIX_0F7E, 897 PREFIX_0F7F, 898 PREFIX_0FAE_REG_0, 899 PREFIX_0FAE_REG_1, 900 PREFIX_0FAE_REG_2, 901 PREFIX_0FAE_REG_3, 902 PREFIX_0FAE_REG_6, 903 PREFIX_0FAE_REG_7, 904 PREFIX_RM_0_0FAE_REG_7, 905 PREFIX_0FB8, 906 PREFIX_0FBC, 907 PREFIX_0FBD, 908 PREFIX_0FC2, 909 PREFIX_0FC3, 910 PREFIX_0FC7_REG_6, 911 PREFIX_0FD0, 912 PREFIX_0FD6, 913 PREFIX_0FE6, 914 PREFIX_0FE7, 915 PREFIX_0FF0, 916 PREFIX_0FF7, 917 PREFIX_0F3810, 918 PREFIX_0F3814, 919 PREFIX_0F3815, 920 PREFIX_0F3817, 921 PREFIX_0F3820, 922 PREFIX_0F3821, 923 PREFIX_0F3822, 924 PREFIX_0F3823, 925 PREFIX_0F3824, 926 PREFIX_0F3825, 927 PREFIX_0F3828, 928 PREFIX_0F3829, 929 PREFIX_0F382A, 930 PREFIX_0F382B, 931 PREFIX_0F3830, 932 PREFIX_0F3831, 933 PREFIX_0F3832, 934 PREFIX_0F3833, 935 PREFIX_0F3834, 936 PREFIX_0F3835, 937 PREFIX_0F3837, 938 PREFIX_0F3838, 939 PREFIX_0F3839, 940 PREFIX_0F383A, 941 PREFIX_0F383B, 942 PREFIX_0F383C, 943 PREFIX_0F383D, 944 PREFIX_0F383E, 945 PREFIX_0F383F, 946 PREFIX_0F3840, 947 PREFIX_0F3841, 948 PREFIX_0F3880, 949 PREFIX_0F3881, 950 PREFIX_0F3882, 951 PREFIX_0F38C8, 952 PREFIX_0F38C9, 953 PREFIX_0F38CA, 954 PREFIX_0F38CB, 955 PREFIX_0F38CC, 956 PREFIX_0F38CD, 957 PREFIX_0F38DB, 958 PREFIX_0F38DC, 959 PREFIX_0F38DD, 960 PREFIX_0F38DE, 961 PREFIX_0F38DF, 962 PREFIX_0F38F0, 963 PREFIX_0F38F1, 964 PREFIX_0F38F6, 965 PREFIX_0F3A08, 966 PREFIX_0F3A09, 967 PREFIX_0F3A0A, 968 PREFIX_0F3A0B, 969 PREFIX_0F3A0C, 970 PREFIX_0F3A0D, 971 PREFIX_0F3A0E, 972 PREFIX_0F3A14, 973 PREFIX_0F3A15, 974 PREFIX_0F3A16, 975 PREFIX_0F3A17, 976 PREFIX_0F3A20, 977 PREFIX_0F3A21, 978 PREFIX_0F3A22, 979 PREFIX_0F3A40, 980 PREFIX_0F3A41, 981 PREFIX_0F3A42, 982 PREFIX_0F3A44, 983 PREFIX_0F3A60, 984 PREFIX_0F3A61, 985 PREFIX_0F3A62, 986 PREFIX_0F3A63, 987 PREFIX_0F3ACC, 988 PREFIX_0F3ADF, 989 PREFIX_VEX_0F10, 990 PREFIX_VEX_0F11, 991 PREFIX_VEX_0F12, 992 PREFIX_VEX_0F16, 993 PREFIX_VEX_0F2A, 994 PREFIX_VEX_0F2C, 995 PREFIX_VEX_0F2D, 996 PREFIX_VEX_0F2E, 997 PREFIX_VEX_0F2F, 998 PREFIX_VEX_0F41, 999 PREFIX_VEX_0F42, 1000 PREFIX_VEX_0F44, 1001 PREFIX_VEX_0F45, 1002 PREFIX_VEX_0F46, 1003 PREFIX_VEX_0F47, 1004 PREFIX_VEX_0F4A, 1005 PREFIX_VEX_0F4B, 1006 PREFIX_VEX_0F51, 1007 PREFIX_VEX_0F52, 1008 PREFIX_VEX_0F53, 1009 PREFIX_VEX_0F58, 1010 PREFIX_VEX_0F59, 1011 PREFIX_VEX_0F5A, 1012 PREFIX_VEX_0F5B, 1013 PREFIX_VEX_0F5C, 1014 PREFIX_VEX_0F5D, 1015 PREFIX_VEX_0F5E, 1016 PREFIX_VEX_0F5F, 1017 PREFIX_VEX_0F60, 1018 PREFIX_VEX_0F61, 1019 PREFIX_VEX_0F62, 1020 PREFIX_VEX_0F63, 1021 PREFIX_VEX_0F64, 1022 PREFIX_VEX_0F65, 1023 PREFIX_VEX_0F66, 1024 PREFIX_VEX_0F67, 1025 PREFIX_VEX_0F68, 1026 PREFIX_VEX_0F69, 1027 PREFIX_VEX_0F6A, 1028 PREFIX_VEX_0F6B, 1029 PREFIX_VEX_0F6C, 1030 PREFIX_VEX_0F6D, 1031 PREFIX_VEX_0F6E, 1032 PREFIX_VEX_0F6F, 1033 PREFIX_VEX_0F70, 1034 PREFIX_VEX_0F71_REG_2, 1035 PREFIX_VEX_0F71_REG_4, 1036 PREFIX_VEX_0F71_REG_6, 1037 PREFIX_VEX_0F72_REG_2, 1038 PREFIX_VEX_0F72_REG_4, 1039 PREFIX_VEX_0F72_REG_6, 1040 PREFIX_VEX_0F73_REG_2, 1041 PREFIX_VEX_0F73_REG_3, 1042 PREFIX_VEX_0F73_REG_6, 1043 PREFIX_VEX_0F73_REG_7, 1044 PREFIX_VEX_0F74, 1045 PREFIX_VEX_0F75, 1046 PREFIX_VEX_0F76, 1047 PREFIX_VEX_0F77, 1048 PREFIX_VEX_0F7C, 1049 PREFIX_VEX_0F7D, 1050 PREFIX_VEX_0F7E, 1051 PREFIX_VEX_0F7F, 1052 PREFIX_VEX_0F90, 1053 PREFIX_VEX_0F91, 1054 PREFIX_VEX_0F92, 1055 PREFIX_VEX_0F93, 1056 PREFIX_VEX_0F98, 1057 PREFIX_VEX_0F99, 1058 PREFIX_VEX_0FC2, 1059 PREFIX_VEX_0FC4, 1060 PREFIX_VEX_0FC5, 1061 PREFIX_VEX_0FD0, 1062 PREFIX_VEX_0FD1, 1063 PREFIX_VEX_0FD2, 1064 PREFIX_VEX_0FD3, 1065 PREFIX_VEX_0FD4, 1066 PREFIX_VEX_0FD5, 1067 PREFIX_VEX_0FD6, 1068 PREFIX_VEX_0FD7, 1069 PREFIX_VEX_0FD8, 1070 PREFIX_VEX_0FD9, 1071 PREFIX_VEX_0FDA, 1072 PREFIX_VEX_0FDB, 1073 PREFIX_VEX_0FDC, 1074 PREFIX_VEX_0FDD, 1075 PREFIX_VEX_0FDE, 1076 PREFIX_VEX_0FDF, 1077 PREFIX_VEX_0FE0, 1078 PREFIX_VEX_0FE1, 1079 PREFIX_VEX_0FE2, 1080 PREFIX_VEX_0FE3, 1081 PREFIX_VEX_0FE4, 1082 PREFIX_VEX_0FE5, 1083 PREFIX_VEX_0FE6, 1084 PREFIX_VEX_0FE7, 1085 PREFIX_VEX_0FE8, 1086 PREFIX_VEX_0FE9, 1087 PREFIX_VEX_0FEA, 1088 PREFIX_VEX_0FEB, 1089 PREFIX_VEX_0FEC, 1090 PREFIX_VEX_0FED, 1091 PREFIX_VEX_0FEE, 1092 PREFIX_VEX_0FEF, 1093 PREFIX_VEX_0FF0, 1094 PREFIX_VEX_0FF1, 1095 PREFIX_VEX_0FF2, 1096 PREFIX_VEX_0FF3, 1097 PREFIX_VEX_0FF4, 1098 PREFIX_VEX_0FF5, 1099 PREFIX_VEX_0FF6, 1100 PREFIX_VEX_0FF7, 1101 PREFIX_VEX_0FF8, 1102 PREFIX_VEX_0FF9, 1103 PREFIX_VEX_0FFA, 1104 PREFIX_VEX_0FFB, 1105 PREFIX_VEX_0FFC, 1106 PREFIX_VEX_0FFD, 1107 PREFIX_VEX_0FFE, 1108 PREFIX_VEX_0F3800, 1109 PREFIX_VEX_0F3801, 1110 PREFIX_VEX_0F3802, 1111 PREFIX_VEX_0F3803, 1112 PREFIX_VEX_0F3804, 1113 PREFIX_VEX_0F3805, 1114 PREFIX_VEX_0F3806, 1115 PREFIX_VEX_0F3807, 1116 PREFIX_VEX_0F3808, 1117 PREFIX_VEX_0F3809, 1118 PREFIX_VEX_0F380A, 1119 PREFIX_VEX_0F380B, 1120 PREFIX_VEX_0F380C, 1121 PREFIX_VEX_0F380D, 1122 PREFIX_VEX_0F380E, 1123 PREFIX_VEX_0F380F, 1124 PREFIX_VEX_0F3813, 1125 PREFIX_VEX_0F3816, 1126 PREFIX_VEX_0F3817, 1127 PREFIX_VEX_0F3818, 1128 PREFIX_VEX_0F3819, 1129 PREFIX_VEX_0F381A, 1130 PREFIX_VEX_0F381C, 1131 PREFIX_VEX_0F381D, 1132 PREFIX_VEX_0F381E, 1133 PREFIX_VEX_0F3820, 1134 PREFIX_VEX_0F3821, 1135 PREFIX_VEX_0F3822, 1136 PREFIX_VEX_0F3823, 1137 PREFIX_VEX_0F3824, 1138 PREFIX_VEX_0F3825, 1139 PREFIX_VEX_0F3828, 1140 PREFIX_VEX_0F3829, 1141 PREFIX_VEX_0F382A, 1142 PREFIX_VEX_0F382B, 1143 PREFIX_VEX_0F382C, 1144 PREFIX_VEX_0F382D, 1145 PREFIX_VEX_0F382E, 1146 PREFIX_VEX_0F382F, 1147 PREFIX_VEX_0F3830, 1148 PREFIX_VEX_0F3831, 1149 PREFIX_VEX_0F3832, 1150 PREFIX_VEX_0F3833, 1151 PREFIX_VEX_0F3834, 1152 PREFIX_VEX_0F3835, 1153 PREFIX_VEX_0F3836, 1154 PREFIX_VEX_0F3837, 1155 PREFIX_VEX_0F3838, 1156 PREFIX_VEX_0F3839, 1157 PREFIX_VEX_0F383A, 1158 PREFIX_VEX_0F383B, 1159 PREFIX_VEX_0F383C, 1160 PREFIX_VEX_0F383D, 1161 PREFIX_VEX_0F383E, 1162 PREFIX_VEX_0F383F, 1163 PREFIX_VEX_0F3840, 1164 PREFIX_VEX_0F3841, 1165 PREFIX_VEX_0F3845, 1166 PREFIX_VEX_0F3846, 1167 PREFIX_VEX_0F3847, 1168 PREFIX_VEX_0F3858, 1169 PREFIX_VEX_0F3859, 1170 PREFIX_VEX_0F385A, 1171 PREFIX_VEX_0F3878, 1172 PREFIX_VEX_0F3879, 1173 PREFIX_VEX_0F388C, 1174 PREFIX_VEX_0F388E, 1175 PREFIX_VEX_0F3890, 1176 PREFIX_VEX_0F3891, 1177 PREFIX_VEX_0F3892, 1178 PREFIX_VEX_0F3893, 1179 PREFIX_VEX_0F3896, 1180 PREFIX_VEX_0F3897, 1181 PREFIX_VEX_0F3898, 1182 PREFIX_VEX_0F3899, 1183 PREFIX_VEX_0F389A, 1184 PREFIX_VEX_0F389B, 1185 PREFIX_VEX_0F389C, 1186 PREFIX_VEX_0F389D, 1187 PREFIX_VEX_0F389E, 1188 PREFIX_VEX_0F389F, 1189 PREFIX_VEX_0F38A6, 1190 PREFIX_VEX_0F38A7, 1191 PREFIX_VEX_0F38A8, 1192 PREFIX_VEX_0F38A9, 1193 PREFIX_VEX_0F38AA, 1194 PREFIX_VEX_0F38AB, 1195 PREFIX_VEX_0F38AC, 1196 PREFIX_VEX_0F38AD, 1197 PREFIX_VEX_0F38AE, 1198 PREFIX_VEX_0F38AF, 1199 PREFIX_VEX_0F38B6, 1200 PREFIX_VEX_0F38B7, 1201 PREFIX_VEX_0F38B8, 1202 PREFIX_VEX_0F38B9, 1203 PREFIX_VEX_0F38BA, 1204 PREFIX_VEX_0F38BB, 1205 PREFIX_VEX_0F38BC, 1206 PREFIX_VEX_0F38BD, 1207 PREFIX_VEX_0F38BE, 1208 PREFIX_VEX_0F38BF, 1209 PREFIX_VEX_0F38DB, 1210 PREFIX_VEX_0F38DC, 1211 PREFIX_VEX_0F38DD, 1212 PREFIX_VEX_0F38DE, 1213 PREFIX_VEX_0F38DF, 1214 PREFIX_VEX_0F38F2, 1215 PREFIX_VEX_0F38F3_REG_1, 1216 PREFIX_VEX_0F38F3_REG_2, 1217 PREFIX_VEX_0F38F3_REG_3, 1218 PREFIX_VEX_0F38F5, 1219 PREFIX_VEX_0F38F6, 1220 PREFIX_VEX_0F38F7, 1221 PREFIX_VEX_0F3A00, 1222 PREFIX_VEX_0F3A01, 1223 PREFIX_VEX_0F3A02, 1224 PREFIX_VEX_0F3A04, 1225 PREFIX_VEX_0F3A05, 1226 PREFIX_VEX_0F3A06, 1227 PREFIX_VEX_0F3A08, 1228 PREFIX_VEX_0F3A09, 1229 PREFIX_VEX_0F3A0A, 1230 PREFIX_VEX_0F3A0B, 1231 PREFIX_VEX_0F3A0C, 1232 PREFIX_VEX_0F3A0D, 1233 PREFIX_VEX_0F3A0E, 1234 PREFIX_VEX_0F3A0F, 1235 PREFIX_VEX_0F3A14, 1236 PREFIX_VEX_0F3A15, 1237 PREFIX_VEX_0F3A16, 1238 PREFIX_VEX_0F3A17, 1239 PREFIX_VEX_0F3A18, 1240 PREFIX_VEX_0F3A19, 1241 PREFIX_VEX_0F3A1D, 1242 PREFIX_VEX_0F3A20, 1243 PREFIX_VEX_0F3A21, 1244 PREFIX_VEX_0F3A22, 1245 PREFIX_VEX_0F3A30, 1246 PREFIX_VEX_0F3A31, 1247 PREFIX_VEX_0F3A32, 1248 PREFIX_VEX_0F3A33, 1249 PREFIX_VEX_0F3A38, 1250 PREFIX_VEX_0F3A39, 1251 PREFIX_VEX_0F3A40, 1252 PREFIX_VEX_0F3A41, 1253 PREFIX_VEX_0F3A42, 1254 PREFIX_VEX_0F3A44, 1255 PREFIX_VEX_0F3A46, 1256 PREFIX_VEX_0F3A48, 1257 PREFIX_VEX_0F3A49, 1258 PREFIX_VEX_0F3A4A, 1259 PREFIX_VEX_0F3A4B, 1260 PREFIX_VEX_0F3A4C, 1261 PREFIX_VEX_0F3A5C, 1262 PREFIX_VEX_0F3A5D, 1263 PREFIX_VEX_0F3A5E, 1264 PREFIX_VEX_0F3A5F, 1265 PREFIX_VEX_0F3A60, 1266 PREFIX_VEX_0F3A61, 1267 PREFIX_VEX_0F3A62, 1268 PREFIX_VEX_0F3A63, 1269 PREFIX_VEX_0F3A68, 1270 PREFIX_VEX_0F3A69, 1271 PREFIX_VEX_0F3A6A, 1272 PREFIX_VEX_0F3A6B, 1273 PREFIX_VEX_0F3A6C, 1274 PREFIX_VEX_0F3A6D, 1275 PREFIX_VEX_0F3A6E, 1276 PREFIX_VEX_0F3A6F, 1277 PREFIX_VEX_0F3A78, 1278 PREFIX_VEX_0F3A79, 1279 PREFIX_VEX_0F3A7A, 1280 PREFIX_VEX_0F3A7B, 1281 PREFIX_VEX_0F3A7C, 1282 PREFIX_VEX_0F3A7D, 1283 PREFIX_VEX_0F3A7E, 1284 PREFIX_VEX_0F3A7F, 1285 PREFIX_VEX_0F3ADF, 1286 PREFIX_VEX_0F3AF0, 1287 1288 PREFIX_EVEX_0F10, 1289 PREFIX_EVEX_0F11, 1290 PREFIX_EVEX_0F12, 1291 PREFIX_EVEX_0F13, 1292 PREFIX_EVEX_0F14, 1293 PREFIX_EVEX_0F15, 1294 PREFIX_EVEX_0F16, 1295 PREFIX_EVEX_0F17, 1296 PREFIX_EVEX_0F28, 1297 PREFIX_EVEX_0F29, 1298 PREFIX_EVEX_0F2A, 1299 PREFIX_EVEX_0F2B, 1300 PREFIX_EVEX_0F2C, 1301 PREFIX_EVEX_0F2D, 1302 PREFIX_EVEX_0F2E, 1303 PREFIX_EVEX_0F2F, 1304 PREFIX_EVEX_0F51, 1305 PREFIX_EVEX_0F54, 1306 PREFIX_EVEX_0F55, 1307 PREFIX_EVEX_0F56, 1308 PREFIX_EVEX_0F57, 1309 PREFIX_EVEX_0F58, 1310 PREFIX_EVEX_0F59, 1311 PREFIX_EVEX_0F5A, 1312 PREFIX_EVEX_0F5B, 1313 PREFIX_EVEX_0F5C, 1314 PREFIX_EVEX_0F5D, 1315 PREFIX_EVEX_0F5E, 1316 PREFIX_EVEX_0F5F, 1317 PREFIX_EVEX_0F60, 1318 PREFIX_EVEX_0F61, 1319 PREFIX_EVEX_0F62, 1320 PREFIX_EVEX_0F63, 1321 PREFIX_EVEX_0F64, 1322 PREFIX_EVEX_0F65, 1323 PREFIX_EVEX_0F66, 1324 PREFIX_EVEX_0F67, 1325 PREFIX_EVEX_0F68, 1326 PREFIX_EVEX_0F69, 1327 PREFIX_EVEX_0F6A, 1328 PREFIX_EVEX_0F6B, 1329 PREFIX_EVEX_0F6C, 1330 PREFIX_EVEX_0F6D, 1331 PREFIX_EVEX_0F6E, 1332 PREFIX_EVEX_0F6F, 1333 PREFIX_EVEX_0F70, 1334 PREFIX_EVEX_0F71_REG_2, 1335 PREFIX_EVEX_0F71_REG_4, 1336 PREFIX_EVEX_0F71_REG_6, 1337 PREFIX_EVEX_0F72_REG_0, 1338 PREFIX_EVEX_0F72_REG_1, 1339 PREFIX_EVEX_0F72_REG_2, 1340 PREFIX_EVEX_0F72_REG_4, 1341 PREFIX_EVEX_0F72_REG_6, 1342 PREFIX_EVEX_0F73_REG_2, 1343 PREFIX_EVEX_0F73_REG_3, 1344 PREFIX_EVEX_0F73_REG_6, 1345 PREFIX_EVEX_0F73_REG_7, 1346 PREFIX_EVEX_0F74, 1347 PREFIX_EVEX_0F75, 1348 PREFIX_EVEX_0F76, 1349 PREFIX_EVEX_0F78, 1350 PREFIX_EVEX_0F79, 1351 PREFIX_EVEX_0F7A, 1352 PREFIX_EVEX_0F7B, 1353 PREFIX_EVEX_0F7E, 1354 PREFIX_EVEX_0F7F, 1355 PREFIX_EVEX_0FC2, 1356 PREFIX_EVEX_0FC4, 1357 PREFIX_EVEX_0FC5, 1358 PREFIX_EVEX_0FC6, 1359 PREFIX_EVEX_0FD1, 1360 PREFIX_EVEX_0FD2, 1361 PREFIX_EVEX_0FD3, 1362 PREFIX_EVEX_0FD4, 1363 PREFIX_EVEX_0FD5, 1364 PREFIX_EVEX_0FD6, 1365 PREFIX_EVEX_0FD8, 1366 PREFIX_EVEX_0FD9, 1367 PREFIX_EVEX_0FDA, 1368 PREFIX_EVEX_0FDB, 1369 PREFIX_EVEX_0FDC, 1370 PREFIX_EVEX_0FDD, 1371 PREFIX_EVEX_0FDE, 1372 PREFIX_EVEX_0FDF, 1373 PREFIX_EVEX_0FE0, 1374 PREFIX_EVEX_0FE1, 1375 PREFIX_EVEX_0FE2, 1376 PREFIX_EVEX_0FE3, 1377 PREFIX_EVEX_0FE4, 1378 PREFIX_EVEX_0FE5, 1379 PREFIX_EVEX_0FE6, 1380 PREFIX_EVEX_0FE7, 1381 PREFIX_EVEX_0FE8, 1382 PREFIX_EVEX_0FE9, 1383 PREFIX_EVEX_0FEA, 1384 PREFIX_EVEX_0FEB, 1385 PREFIX_EVEX_0FEC, 1386 PREFIX_EVEX_0FED, 1387 PREFIX_EVEX_0FEE, 1388 PREFIX_EVEX_0FEF, 1389 PREFIX_EVEX_0FF1, 1390 PREFIX_EVEX_0FF2, 1391 PREFIX_EVEX_0FF3, 1392 PREFIX_EVEX_0FF4, 1393 PREFIX_EVEX_0FF5, 1394 PREFIX_EVEX_0FF6, 1395 PREFIX_EVEX_0FF8, 1396 PREFIX_EVEX_0FF9, 1397 PREFIX_EVEX_0FFA, 1398 PREFIX_EVEX_0FFB, 1399 PREFIX_EVEX_0FFC, 1400 PREFIX_EVEX_0FFD, 1401 PREFIX_EVEX_0FFE, 1402 PREFIX_EVEX_0F3800, 1403 PREFIX_EVEX_0F3804, 1404 PREFIX_EVEX_0F380B, 1405 PREFIX_EVEX_0F380C, 1406 PREFIX_EVEX_0F380D, 1407 PREFIX_EVEX_0F3810, 1408 PREFIX_EVEX_0F3811, 1409 PREFIX_EVEX_0F3812, 1410 PREFIX_EVEX_0F3813, 1411 PREFIX_EVEX_0F3814, 1412 PREFIX_EVEX_0F3815, 1413 PREFIX_EVEX_0F3816, 1414 PREFIX_EVEX_0F3818, 1415 PREFIX_EVEX_0F3819, 1416 PREFIX_EVEX_0F381A, 1417 PREFIX_EVEX_0F381B, 1418 PREFIX_EVEX_0F381C, 1419 PREFIX_EVEX_0F381D, 1420 PREFIX_EVEX_0F381E, 1421 PREFIX_EVEX_0F381F, 1422 PREFIX_EVEX_0F3820, 1423 PREFIX_EVEX_0F3821, 1424 PREFIX_EVEX_0F3822, 1425 PREFIX_EVEX_0F3823, 1426 PREFIX_EVEX_0F3824, 1427 PREFIX_EVEX_0F3825, 1428 PREFIX_EVEX_0F3826, 1429 PREFIX_EVEX_0F3827, 1430 PREFIX_EVEX_0F3828, 1431 PREFIX_EVEX_0F3829, 1432 PREFIX_EVEX_0F382A, 1433 PREFIX_EVEX_0F382B, 1434 PREFIX_EVEX_0F382C, 1435 PREFIX_EVEX_0F382D, 1436 PREFIX_EVEX_0F3830, 1437 PREFIX_EVEX_0F3831, 1438 PREFIX_EVEX_0F3832, 1439 PREFIX_EVEX_0F3833, 1440 PREFIX_EVEX_0F3834, 1441 PREFIX_EVEX_0F3835, 1442 PREFIX_EVEX_0F3836, 1443 PREFIX_EVEX_0F3837, 1444 PREFIX_EVEX_0F3838, 1445 PREFIX_EVEX_0F3839, 1446 PREFIX_EVEX_0F383A, 1447 PREFIX_EVEX_0F383B, 1448 PREFIX_EVEX_0F383C, 1449 PREFIX_EVEX_0F383D, 1450 PREFIX_EVEX_0F383E, 1451 PREFIX_EVEX_0F383F, 1452 PREFIX_EVEX_0F3840, 1453 PREFIX_EVEX_0F3842, 1454 PREFIX_EVEX_0F3843, 1455 PREFIX_EVEX_0F3844, 1456 PREFIX_EVEX_0F3845, 1457 PREFIX_EVEX_0F3846, 1458 PREFIX_EVEX_0F3847, 1459 PREFIX_EVEX_0F384C, 1460 PREFIX_EVEX_0F384D, 1461 PREFIX_EVEX_0F384E, 1462 PREFIX_EVEX_0F384F, 1463 PREFIX_EVEX_0F3858, 1464 PREFIX_EVEX_0F3859, 1465 PREFIX_EVEX_0F385A, 1466 PREFIX_EVEX_0F385B, 1467 PREFIX_EVEX_0F3864, 1468 PREFIX_EVEX_0F3865, 1469 PREFIX_EVEX_0F3866, 1470 PREFIX_EVEX_0F3875, 1471 PREFIX_EVEX_0F3876, 1472 PREFIX_EVEX_0F3877, 1473 PREFIX_EVEX_0F3878, 1474 PREFIX_EVEX_0F3879, 1475 PREFIX_EVEX_0F387A, 1476 PREFIX_EVEX_0F387B, 1477 PREFIX_EVEX_0F387C, 1478 PREFIX_EVEX_0F387D, 1479 PREFIX_EVEX_0F387E, 1480 PREFIX_EVEX_0F387F, 1481 PREFIX_EVEX_0F3883, 1482 PREFIX_EVEX_0F3888, 1483 PREFIX_EVEX_0F3889, 1484 PREFIX_EVEX_0F388A, 1485 PREFIX_EVEX_0F388B, 1486 PREFIX_EVEX_0F388D, 1487 PREFIX_EVEX_0F3890, 1488 PREFIX_EVEX_0F3891, 1489 PREFIX_EVEX_0F3892, 1490 PREFIX_EVEX_0F3893, 1491 PREFIX_EVEX_0F3896, 1492 PREFIX_EVEX_0F3897, 1493 PREFIX_EVEX_0F3898, 1494 PREFIX_EVEX_0F3899, 1495 PREFIX_EVEX_0F389A, 1496 PREFIX_EVEX_0F389B, 1497 PREFIX_EVEX_0F389C, 1498 PREFIX_EVEX_0F389D, 1499 PREFIX_EVEX_0F389E, 1500 PREFIX_EVEX_0F389F, 1501 PREFIX_EVEX_0F38A0, 1502 PREFIX_EVEX_0F38A1, 1503 PREFIX_EVEX_0F38A2, 1504 PREFIX_EVEX_0F38A3, 1505 PREFIX_EVEX_0F38A6, 1506 PREFIX_EVEX_0F38A7, 1507 PREFIX_EVEX_0F38A8, 1508 PREFIX_EVEX_0F38A9, 1509 PREFIX_EVEX_0F38AA, 1510 PREFIX_EVEX_0F38AB, 1511 PREFIX_EVEX_0F38AC, 1512 PREFIX_EVEX_0F38AD, 1513 PREFIX_EVEX_0F38AE, 1514 PREFIX_EVEX_0F38AF, 1515 PREFIX_EVEX_0F38B4, 1516 PREFIX_EVEX_0F38B5, 1517 PREFIX_EVEX_0F38B6, 1518 PREFIX_EVEX_0F38B7, 1519 PREFIX_EVEX_0F38B8, 1520 PREFIX_EVEX_0F38B9, 1521 PREFIX_EVEX_0F38BA, 1522 PREFIX_EVEX_0F38BB, 1523 PREFIX_EVEX_0F38BC, 1524 PREFIX_EVEX_0F38BD, 1525 PREFIX_EVEX_0F38BE, 1526 PREFIX_EVEX_0F38BF, 1527 PREFIX_EVEX_0F38C4, 1528 PREFIX_EVEX_0F38C6_REG_1, 1529 PREFIX_EVEX_0F38C6_REG_2, 1530 PREFIX_EVEX_0F38C6_REG_5, 1531 PREFIX_EVEX_0F38C6_REG_6, 1532 PREFIX_EVEX_0F38C7_REG_1, 1533 PREFIX_EVEX_0F38C7_REG_2, 1534 PREFIX_EVEX_0F38C7_REG_5, 1535 PREFIX_EVEX_0F38C7_REG_6, 1536 PREFIX_EVEX_0F38C8, 1537 PREFIX_EVEX_0F38CA, 1538 PREFIX_EVEX_0F38CB, 1539 PREFIX_EVEX_0F38CC, 1540 PREFIX_EVEX_0F38CD, 1541 1542 PREFIX_EVEX_0F3A00, 1543 PREFIX_EVEX_0F3A01, 1544 PREFIX_EVEX_0F3A03, 1545 PREFIX_EVEX_0F3A04, 1546 PREFIX_EVEX_0F3A05, 1547 PREFIX_EVEX_0F3A08, 1548 PREFIX_EVEX_0F3A09, 1549 PREFIX_EVEX_0F3A0A, 1550 PREFIX_EVEX_0F3A0B, 1551 PREFIX_EVEX_0F3A0F, 1552 PREFIX_EVEX_0F3A14, 1553 PREFIX_EVEX_0F3A15, 1554 PREFIX_EVEX_0F3A16, 1555 PREFIX_EVEX_0F3A17, 1556 PREFIX_EVEX_0F3A18, 1557 PREFIX_EVEX_0F3A19, 1558 PREFIX_EVEX_0F3A1A, 1559 PREFIX_EVEX_0F3A1B, 1560 PREFIX_EVEX_0F3A1D, 1561 PREFIX_EVEX_0F3A1E, 1562 PREFIX_EVEX_0F3A1F, 1563 PREFIX_EVEX_0F3A20, 1564 PREFIX_EVEX_0F3A21, 1565 PREFIX_EVEX_0F3A22, 1566 PREFIX_EVEX_0F3A23, 1567 PREFIX_EVEX_0F3A25, 1568 PREFIX_EVEX_0F3A26, 1569 PREFIX_EVEX_0F3A27, 1570 PREFIX_EVEX_0F3A38, 1571 PREFIX_EVEX_0F3A39, 1572 PREFIX_EVEX_0F3A3A, 1573 PREFIX_EVEX_0F3A3B, 1574 PREFIX_EVEX_0F3A3E, 1575 PREFIX_EVEX_0F3A3F, 1576 PREFIX_EVEX_0F3A42, 1577 PREFIX_EVEX_0F3A43, 1578 PREFIX_EVEX_0F3A50, 1579 PREFIX_EVEX_0F3A51, 1580 PREFIX_EVEX_0F3A54, 1581 PREFIX_EVEX_0F3A55, 1582 PREFIX_EVEX_0F3A56, 1583 PREFIX_EVEX_0F3A57, 1584 PREFIX_EVEX_0F3A66, 1585 PREFIX_EVEX_0F3A67 1586 }; 1587 1588 enum 1589 { 1590 X86_64_06 = 0, 1591 X86_64_07, 1592 X86_64_0D, 1593 X86_64_16, 1594 X86_64_17, 1595 X86_64_1E, 1596 X86_64_1F, 1597 X86_64_27, 1598 X86_64_2F, 1599 X86_64_37, 1600 X86_64_3F, 1601 X86_64_60, 1602 X86_64_61, 1603 X86_64_62, 1604 X86_64_63, 1605 X86_64_6D, 1606 X86_64_6F, 1607 X86_64_9A, 1608 X86_64_C4, 1609 X86_64_C5, 1610 X86_64_CE, 1611 X86_64_D4, 1612 X86_64_D5, 1613 X86_64_EA, 1614 X86_64_0F01_REG_0, 1615 X86_64_0F01_REG_1, 1616 X86_64_0F01_REG_2, 1617 X86_64_0F01_REG_3 1618 }; 1619 1620 enum 1621 { 1622 THREE_BYTE_0F38 = 0, 1623 THREE_BYTE_0F3A, 1624 THREE_BYTE_0F7A 1625 }; 1626 1627 enum 1628 { 1629 XOP_08 = 0, 1630 XOP_09, 1631 XOP_0A 1632 }; 1633 1634 enum 1635 { 1636 VEX_0F = 0, 1637 VEX_0F38, 1638 VEX_0F3A 1639 }; 1640 1641 enum 1642 { 1643 EVEX_0F = 0, 1644 EVEX_0F38, 1645 EVEX_0F3A 1646 }; 1647 1648 enum 1649 { 1650 VEX_LEN_0F10_P_1 = 0, 1651 VEX_LEN_0F10_P_3, 1652 VEX_LEN_0F11_P_1, 1653 VEX_LEN_0F11_P_3, 1654 VEX_LEN_0F12_P_0_M_0, 1655 VEX_LEN_0F12_P_0_M_1, 1656 VEX_LEN_0F12_P_2, 1657 VEX_LEN_0F13_M_0, 1658 VEX_LEN_0F16_P_0_M_0, 1659 VEX_LEN_0F16_P_0_M_1, 1660 VEX_LEN_0F16_P_2, 1661 VEX_LEN_0F17_M_0, 1662 VEX_LEN_0F2A_P_1, 1663 VEX_LEN_0F2A_P_3, 1664 VEX_LEN_0F2C_P_1, 1665 VEX_LEN_0F2C_P_3, 1666 VEX_LEN_0F2D_P_1, 1667 VEX_LEN_0F2D_P_3, 1668 VEX_LEN_0F2E_P_0, 1669 VEX_LEN_0F2E_P_2, 1670 VEX_LEN_0F2F_P_0, 1671 VEX_LEN_0F2F_P_2, 1672 VEX_LEN_0F41_P_0, 1673 VEX_LEN_0F41_P_2, 1674 VEX_LEN_0F42_P_0, 1675 VEX_LEN_0F42_P_2, 1676 VEX_LEN_0F44_P_0, 1677 VEX_LEN_0F44_P_2, 1678 VEX_LEN_0F45_P_0, 1679 VEX_LEN_0F45_P_2, 1680 VEX_LEN_0F46_P_0, 1681 VEX_LEN_0F46_P_2, 1682 VEX_LEN_0F47_P_0, 1683 VEX_LEN_0F47_P_2, 1684 VEX_LEN_0F4A_P_0, 1685 VEX_LEN_0F4A_P_2, 1686 VEX_LEN_0F4B_P_0, 1687 VEX_LEN_0F4B_P_2, 1688 VEX_LEN_0F51_P_1, 1689 VEX_LEN_0F51_P_3, 1690 VEX_LEN_0F52_P_1, 1691 VEX_LEN_0F53_P_1, 1692 VEX_LEN_0F58_P_1, 1693 VEX_LEN_0F58_P_3, 1694 VEX_LEN_0F59_P_1, 1695 VEX_LEN_0F59_P_3, 1696 VEX_LEN_0F5A_P_1, 1697 VEX_LEN_0F5A_P_3, 1698 VEX_LEN_0F5C_P_1, 1699 VEX_LEN_0F5C_P_3, 1700 VEX_LEN_0F5D_P_1, 1701 VEX_LEN_0F5D_P_3, 1702 VEX_LEN_0F5E_P_1, 1703 VEX_LEN_0F5E_P_3, 1704 VEX_LEN_0F5F_P_1, 1705 VEX_LEN_0F5F_P_3, 1706 VEX_LEN_0F6E_P_2, 1707 VEX_LEN_0F7E_P_1, 1708 VEX_LEN_0F7E_P_2, 1709 VEX_LEN_0F90_P_0, 1710 VEX_LEN_0F90_P_2, 1711 VEX_LEN_0F91_P_0, 1712 VEX_LEN_0F91_P_2, 1713 VEX_LEN_0F92_P_0, 1714 VEX_LEN_0F92_P_2, 1715 VEX_LEN_0F92_P_3, 1716 VEX_LEN_0F93_P_0, 1717 VEX_LEN_0F93_P_2, 1718 VEX_LEN_0F93_P_3, 1719 VEX_LEN_0F98_P_0, 1720 VEX_LEN_0F98_P_2, 1721 VEX_LEN_0F99_P_0, 1722 VEX_LEN_0F99_P_2, 1723 VEX_LEN_0FAE_R_2_M_0, 1724 VEX_LEN_0FAE_R_3_M_0, 1725 VEX_LEN_0FC2_P_1, 1726 VEX_LEN_0FC2_P_3, 1727 VEX_LEN_0FC4_P_2, 1728 VEX_LEN_0FC5_P_2, 1729 VEX_LEN_0FD6_P_2, 1730 VEX_LEN_0FF7_P_2, 1731 VEX_LEN_0F3816_P_2, 1732 VEX_LEN_0F3819_P_2, 1733 VEX_LEN_0F381A_P_2_M_0, 1734 VEX_LEN_0F3836_P_2, 1735 VEX_LEN_0F3841_P_2, 1736 VEX_LEN_0F385A_P_2_M_0, 1737 VEX_LEN_0F38DB_P_2, 1738 VEX_LEN_0F38DC_P_2, 1739 VEX_LEN_0F38DD_P_2, 1740 VEX_LEN_0F38DE_P_2, 1741 VEX_LEN_0F38DF_P_2, 1742 VEX_LEN_0F38F2_P_0, 1743 VEX_LEN_0F38F3_R_1_P_0, 1744 VEX_LEN_0F38F3_R_2_P_0, 1745 VEX_LEN_0F38F3_R_3_P_0, 1746 VEX_LEN_0F38F5_P_0, 1747 VEX_LEN_0F38F5_P_1, 1748 VEX_LEN_0F38F5_P_3, 1749 VEX_LEN_0F38F6_P_3, 1750 VEX_LEN_0F38F7_P_0, 1751 VEX_LEN_0F38F7_P_1, 1752 VEX_LEN_0F38F7_P_2, 1753 VEX_LEN_0F38F7_P_3, 1754 VEX_LEN_0F3A00_P_2, 1755 VEX_LEN_0F3A01_P_2, 1756 VEX_LEN_0F3A06_P_2, 1757 VEX_LEN_0F3A0A_P_2, 1758 VEX_LEN_0F3A0B_P_2, 1759 VEX_LEN_0F3A14_P_2, 1760 VEX_LEN_0F3A15_P_2, 1761 VEX_LEN_0F3A16_P_2, 1762 VEX_LEN_0F3A17_P_2, 1763 VEX_LEN_0F3A18_P_2, 1764 VEX_LEN_0F3A19_P_2, 1765 VEX_LEN_0F3A20_P_2, 1766 VEX_LEN_0F3A21_P_2, 1767 VEX_LEN_0F3A22_P_2, 1768 VEX_LEN_0F3A30_P_2, 1769 VEX_LEN_0F3A31_P_2, 1770 VEX_LEN_0F3A32_P_2, 1771 VEX_LEN_0F3A33_P_2, 1772 VEX_LEN_0F3A38_P_2, 1773 VEX_LEN_0F3A39_P_2, 1774 VEX_LEN_0F3A41_P_2, 1775 VEX_LEN_0F3A44_P_2, 1776 VEX_LEN_0F3A46_P_2, 1777 VEX_LEN_0F3A60_P_2, 1778 VEX_LEN_0F3A61_P_2, 1779 VEX_LEN_0F3A62_P_2, 1780 VEX_LEN_0F3A63_P_2, 1781 VEX_LEN_0F3A6A_P_2, 1782 VEX_LEN_0F3A6B_P_2, 1783 VEX_LEN_0F3A6E_P_2, 1784 VEX_LEN_0F3A6F_P_2, 1785 VEX_LEN_0F3A7A_P_2, 1786 VEX_LEN_0F3A7B_P_2, 1787 VEX_LEN_0F3A7E_P_2, 1788 VEX_LEN_0F3A7F_P_2, 1789 VEX_LEN_0F3ADF_P_2, 1790 VEX_LEN_0F3AF0_P_3, 1791 VEX_LEN_0FXOP_08_CC, 1792 VEX_LEN_0FXOP_08_CD, 1793 VEX_LEN_0FXOP_08_CE, 1794 VEX_LEN_0FXOP_08_CF, 1795 VEX_LEN_0FXOP_08_EC, 1796 VEX_LEN_0FXOP_08_ED, 1797 VEX_LEN_0FXOP_08_EE, 1798 VEX_LEN_0FXOP_08_EF, 1799 VEX_LEN_0FXOP_09_80, 1800 VEX_LEN_0FXOP_09_81 1801 }; 1802 1803 enum 1804 { 1805 VEX_W_0F10_P_0 = 0, 1806 VEX_W_0F10_P_1, 1807 VEX_W_0F10_P_2, 1808 VEX_W_0F10_P_3, 1809 VEX_W_0F11_P_0, 1810 VEX_W_0F11_P_1, 1811 VEX_W_0F11_P_2, 1812 VEX_W_0F11_P_3, 1813 VEX_W_0F12_P_0_M_0, 1814 VEX_W_0F12_P_0_M_1, 1815 VEX_W_0F12_P_1, 1816 VEX_W_0F12_P_2, 1817 VEX_W_0F12_P_3, 1818 VEX_W_0F13_M_0, 1819 VEX_W_0F14, 1820 VEX_W_0F15, 1821 VEX_W_0F16_P_0_M_0, 1822 VEX_W_0F16_P_0_M_1, 1823 VEX_W_0F16_P_1, 1824 VEX_W_0F16_P_2, 1825 VEX_W_0F17_M_0, 1826 VEX_W_0F28, 1827 VEX_W_0F29, 1828 VEX_W_0F2B_M_0, 1829 VEX_W_0F2E_P_0, 1830 VEX_W_0F2E_P_2, 1831 VEX_W_0F2F_P_0, 1832 VEX_W_0F2F_P_2, 1833 VEX_W_0F41_P_0_LEN_1, 1834 VEX_W_0F41_P_2_LEN_1, 1835 VEX_W_0F42_P_0_LEN_1, 1836 VEX_W_0F42_P_2_LEN_1, 1837 VEX_W_0F44_P_0_LEN_0, 1838 VEX_W_0F44_P_2_LEN_0, 1839 VEX_W_0F45_P_0_LEN_1, 1840 VEX_W_0F45_P_2_LEN_1, 1841 VEX_W_0F46_P_0_LEN_1, 1842 VEX_W_0F46_P_2_LEN_1, 1843 VEX_W_0F47_P_0_LEN_1, 1844 VEX_W_0F47_P_2_LEN_1, 1845 VEX_W_0F4A_P_0_LEN_1, 1846 VEX_W_0F4A_P_2_LEN_1, 1847 VEX_W_0F4B_P_0_LEN_1, 1848 VEX_W_0F4B_P_2_LEN_1, 1849 VEX_W_0F50_M_0, 1850 VEX_W_0F51_P_0, 1851 VEX_W_0F51_P_1, 1852 VEX_W_0F51_P_2, 1853 VEX_W_0F51_P_3, 1854 VEX_W_0F52_P_0, 1855 VEX_W_0F52_P_1, 1856 VEX_W_0F53_P_0, 1857 VEX_W_0F53_P_1, 1858 VEX_W_0F58_P_0, 1859 VEX_W_0F58_P_1, 1860 VEX_W_0F58_P_2, 1861 VEX_W_0F58_P_3, 1862 VEX_W_0F59_P_0, 1863 VEX_W_0F59_P_1, 1864 VEX_W_0F59_P_2, 1865 VEX_W_0F59_P_3, 1866 VEX_W_0F5A_P_0, 1867 VEX_W_0F5A_P_1, 1868 VEX_W_0F5A_P_3, 1869 VEX_W_0F5B_P_0, 1870 VEX_W_0F5B_P_1, 1871 VEX_W_0F5B_P_2, 1872 VEX_W_0F5C_P_0, 1873 VEX_W_0F5C_P_1, 1874 VEX_W_0F5C_P_2, 1875 VEX_W_0F5C_P_3, 1876 VEX_W_0F5D_P_0, 1877 VEX_W_0F5D_P_1, 1878 VEX_W_0F5D_P_2, 1879 VEX_W_0F5D_P_3, 1880 VEX_W_0F5E_P_0, 1881 VEX_W_0F5E_P_1, 1882 VEX_W_0F5E_P_2, 1883 VEX_W_0F5E_P_3, 1884 VEX_W_0F5F_P_0, 1885 VEX_W_0F5F_P_1, 1886 VEX_W_0F5F_P_2, 1887 VEX_W_0F5F_P_3, 1888 VEX_W_0F60_P_2, 1889 VEX_W_0F61_P_2, 1890 VEX_W_0F62_P_2, 1891 VEX_W_0F63_P_2, 1892 VEX_W_0F64_P_2, 1893 VEX_W_0F65_P_2, 1894 VEX_W_0F66_P_2, 1895 VEX_W_0F67_P_2, 1896 VEX_W_0F68_P_2, 1897 VEX_W_0F69_P_2, 1898 VEX_W_0F6A_P_2, 1899 VEX_W_0F6B_P_2, 1900 VEX_W_0F6C_P_2, 1901 VEX_W_0F6D_P_2, 1902 VEX_W_0F6F_P_1, 1903 VEX_W_0F6F_P_2, 1904 VEX_W_0F70_P_1, 1905 VEX_W_0F70_P_2, 1906 VEX_W_0F70_P_3, 1907 VEX_W_0F71_R_2_P_2, 1908 VEX_W_0F71_R_4_P_2, 1909 VEX_W_0F71_R_6_P_2, 1910 VEX_W_0F72_R_2_P_2, 1911 VEX_W_0F72_R_4_P_2, 1912 VEX_W_0F72_R_6_P_2, 1913 VEX_W_0F73_R_2_P_2, 1914 VEX_W_0F73_R_3_P_2, 1915 VEX_W_0F73_R_6_P_2, 1916 VEX_W_0F73_R_7_P_2, 1917 VEX_W_0F74_P_2, 1918 VEX_W_0F75_P_2, 1919 VEX_W_0F76_P_2, 1920 VEX_W_0F77_P_0, 1921 VEX_W_0F7C_P_2, 1922 VEX_W_0F7C_P_3, 1923 VEX_W_0F7D_P_2, 1924 VEX_W_0F7D_P_3, 1925 VEX_W_0F7E_P_1, 1926 VEX_W_0F7F_P_1, 1927 VEX_W_0F7F_P_2, 1928 VEX_W_0F90_P_0_LEN_0, 1929 VEX_W_0F90_P_2_LEN_0, 1930 VEX_W_0F91_P_0_LEN_0, 1931 VEX_W_0F91_P_2_LEN_0, 1932 VEX_W_0F92_P_0_LEN_0, 1933 VEX_W_0F92_P_2_LEN_0, 1934 VEX_W_0F92_P_3_LEN_0, 1935 VEX_W_0F93_P_0_LEN_0, 1936 VEX_W_0F93_P_2_LEN_0, 1937 VEX_W_0F93_P_3_LEN_0, 1938 VEX_W_0F98_P_0_LEN_0, 1939 VEX_W_0F98_P_2_LEN_0, 1940 VEX_W_0F99_P_0_LEN_0, 1941 VEX_W_0F99_P_2_LEN_0, 1942 VEX_W_0FAE_R_2_M_0, 1943 VEX_W_0FAE_R_3_M_0, 1944 VEX_W_0FC2_P_0, 1945 VEX_W_0FC2_P_1, 1946 VEX_W_0FC2_P_2, 1947 VEX_W_0FC2_P_3, 1948 VEX_W_0FC4_P_2, 1949 VEX_W_0FC5_P_2, 1950 VEX_W_0FD0_P_2, 1951 VEX_W_0FD0_P_3, 1952 VEX_W_0FD1_P_2, 1953 VEX_W_0FD2_P_2, 1954 VEX_W_0FD3_P_2, 1955 VEX_W_0FD4_P_2, 1956 VEX_W_0FD5_P_2, 1957 VEX_W_0FD6_P_2, 1958 VEX_W_0FD7_P_2_M_1, 1959 VEX_W_0FD8_P_2, 1960 VEX_W_0FD9_P_2, 1961 VEX_W_0FDA_P_2, 1962 VEX_W_0FDB_P_2, 1963 VEX_W_0FDC_P_2, 1964 VEX_W_0FDD_P_2, 1965 VEX_W_0FDE_P_2, 1966 VEX_W_0FDF_P_2, 1967 VEX_W_0FE0_P_2, 1968 VEX_W_0FE1_P_2, 1969 VEX_W_0FE2_P_2, 1970 VEX_W_0FE3_P_2, 1971 VEX_W_0FE4_P_2, 1972 VEX_W_0FE5_P_2, 1973 VEX_W_0FE6_P_1, 1974 VEX_W_0FE6_P_2, 1975 VEX_W_0FE6_P_3, 1976 VEX_W_0FE7_P_2_M_0, 1977 VEX_W_0FE8_P_2, 1978 VEX_W_0FE9_P_2, 1979 VEX_W_0FEA_P_2, 1980 VEX_W_0FEB_P_2, 1981 VEX_W_0FEC_P_2, 1982 VEX_W_0FED_P_2, 1983 VEX_W_0FEE_P_2, 1984 VEX_W_0FEF_P_2, 1985 VEX_W_0FF0_P_3_M_0, 1986 VEX_W_0FF1_P_2, 1987 VEX_W_0FF2_P_2, 1988 VEX_W_0FF3_P_2, 1989 VEX_W_0FF4_P_2, 1990 VEX_W_0FF5_P_2, 1991 VEX_W_0FF6_P_2, 1992 VEX_W_0FF7_P_2, 1993 VEX_W_0FF8_P_2, 1994 VEX_W_0FF9_P_2, 1995 VEX_W_0FFA_P_2, 1996 VEX_W_0FFB_P_2, 1997 VEX_W_0FFC_P_2, 1998 VEX_W_0FFD_P_2, 1999 VEX_W_0FFE_P_2, 2000 VEX_W_0F3800_P_2, 2001 VEX_W_0F3801_P_2, 2002 VEX_W_0F3802_P_2, 2003 VEX_W_0F3803_P_2, 2004 VEX_W_0F3804_P_2, 2005 VEX_W_0F3805_P_2, 2006 VEX_W_0F3806_P_2, 2007 VEX_W_0F3807_P_2, 2008 VEX_W_0F3808_P_2, 2009 VEX_W_0F3809_P_2, 2010 VEX_W_0F380A_P_2, 2011 VEX_W_0F380B_P_2, 2012 VEX_W_0F380C_P_2, 2013 VEX_W_0F380D_P_2, 2014 VEX_W_0F380E_P_2, 2015 VEX_W_0F380F_P_2, 2016 VEX_W_0F3816_P_2, 2017 VEX_W_0F3817_P_2, 2018 VEX_W_0F3818_P_2, 2019 VEX_W_0F3819_P_2, 2020 VEX_W_0F381A_P_2_M_0, 2021 VEX_W_0F381C_P_2, 2022 VEX_W_0F381D_P_2, 2023 VEX_W_0F381E_P_2, 2024 VEX_W_0F3820_P_2, 2025 VEX_W_0F3821_P_2, 2026 VEX_W_0F3822_P_2, 2027 VEX_W_0F3823_P_2, 2028 VEX_W_0F3824_P_2, 2029 VEX_W_0F3825_P_2, 2030 VEX_W_0F3828_P_2, 2031 VEX_W_0F3829_P_2, 2032 VEX_W_0F382A_P_2_M_0, 2033 VEX_W_0F382B_P_2, 2034 VEX_W_0F382C_P_2_M_0, 2035 VEX_W_0F382D_P_2_M_0, 2036 VEX_W_0F382E_P_2_M_0, 2037 VEX_W_0F382F_P_2_M_0, 2038 VEX_W_0F3830_P_2, 2039 VEX_W_0F3831_P_2, 2040 VEX_W_0F3832_P_2, 2041 VEX_W_0F3833_P_2, 2042 VEX_W_0F3834_P_2, 2043 VEX_W_0F3835_P_2, 2044 VEX_W_0F3836_P_2, 2045 VEX_W_0F3837_P_2, 2046 VEX_W_0F3838_P_2, 2047 VEX_W_0F3839_P_2, 2048 VEX_W_0F383A_P_2, 2049 VEX_W_0F383B_P_2, 2050 VEX_W_0F383C_P_2, 2051 VEX_W_0F383D_P_2, 2052 VEX_W_0F383E_P_2, 2053 VEX_W_0F383F_P_2, 2054 VEX_W_0F3840_P_2, 2055 VEX_W_0F3841_P_2, 2056 VEX_W_0F3846_P_2, 2057 VEX_W_0F3858_P_2, 2058 VEX_W_0F3859_P_2, 2059 VEX_W_0F385A_P_2_M_0, 2060 VEX_W_0F3878_P_2, 2061 VEX_W_0F3879_P_2, 2062 VEX_W_0F38DB_P_2, 2063 VEX_W_0F38DC_P_2, 2064 VEX_W_0F38DD_P_2, 2065 VEX_W_0F38DE_P_2, 2066 VEX_W_0F38DF_P_2, 2067 VEX_W_0F3A00_P_2, 2068 VEX_W_0F3A01_P_2, 2069 VEX_W_0F3A02_P_2, 2070 VEX_W_0F3A04_P_2, 2071 VEX_W_0F3A05_P_2, 2072 VEX_W_0F3A06_P_2, 2073 VEX_W_0F3A08_P_2, 2074 VEX_W_0F3A09_P_2, 2075 VEX_W_0F3A0A_P_2, 2076 VEX_W_0F3A0B_P_2, 2077 VEX_W_0F3A0C_P_2, 2078 VEX_W_0F3A0D_P_2, 2079 VEX_W_0F3A0E_P_2, 2080 VEX_W_0F3A0F_P_2, 2081 VEX_W_0F3A14_P_2, 2082 VEX_W_0F3A15_P_2, 2083 VEX_W_0F3A18_P_2, 2084 VEX_W_0F3A19_P_2, 2085 VEX_W_0F3A20_P_2, 2086 VEX_W_0F3A21_P_2, 2087 VEX_W_0F3A30_P_2_LEN_0, 2088 VEX_W_0F3A31_P_2_LEN_0, 2089 VEX_W_0F3A32_P_2_LEN_0, 2090 VEX_W_0F3A33_P_2_LEN_0, 2091 VEX_W_0F3A38_P_2, 2092 VEX_W_0F3A39_P_2, 2093 VEX_W_0F3A40_P_2, 2094 VEX_W_0F3A41_P_2, 2095 VEX_W_0F3A42_P_2, 2096 VEX_W_0F3A44_P_2, 2097 VEX_W_0F3A46_P_2, 2098 VEX_W_0F3A48_P_2, 2099 VEX_W_0F3A49_P_2, 2100 VEX_W_0F3A4A_P_2, 2101 VEX_W_0F3A4B_P_2, 2102 VEX_W_0F3A4C_P_2, 2103 VEX_W_0F3A60_P_2, 2104 VEX_W_0F3A61_P_2, 2105 VEX_W_0F3A62_P_2, 2106 VEX_W_0F3A63_P_2, 2107 VEX_W_0F3ADF_P_2, 2108 2109 EVEX_W_0F10_P_0, 2110 EVEX_W_0F10_P_1_M_0, 2111 EVEX_W_0F10_P_1_M_1, 2112 EVEX_W_0F10_P_2, 2113 EVEX_W_0F10_P_3_M_0, 2114 EVEX_W_0F10_P_3_M_1, 2115 EVEX_W_0F11_P_0, 2116 EVEX_W_0F11_P_1_M_0, 2117 EVEX_W_0F11_P_1_M_1, 2118 EVEX_W_0F11_P_2, 2119 EVEX_W_0F11_P_3_M_0, 2120 EVEX_W_0F11_P_3_M_1, 2121 EVEX_W_0F12_P_0_M_0, 2122 EVEX_W_0F12_P_0_M_1, 2123 EVEX_W_0F12_P_1, 2124 EVEX_W_0F12_P_2, 2125 EVEX_W_0F12_P_3, 2126 EVEX_W_0F13_P_0, 2127 EVEX_W_0F13_P_2, 2128 EVEX_W_0F14_P_0, 2129 EVEX_W_0F14_P_2, 2130 EVEX_W_0F15_P_0, 2131 EVEX_W_0F15_P_2, 2132 EVEX_W_0F16_P_0_M_0, 2133 EVEX_W_0F16_P_0_M_1, 2134 EVEX_W_0F16_P_1, 2135 EVEX_W_0F16_P_2, 2136 EVEX_W_0F17_P_0, 2137 EVEX_W_0F17_P_2, 2138 EVEX_W_0F28_P_0, 2139 EVEX_W_0F28_P_2, 2140 EVEX_W_0F29_P_0, 2141 EVEX_W_0F29_P_2, 2142 EVEX_W_0F2A_P_1, 2143 EVEX_W_0F2A_P_3, 2144 EVEX_W_0F2B_P_0, 2145 EVEX_W_0F2B_P_2, 2146 EVEX_W_0F2E_P_0, 2147 EVEX_W_0F2E_P_2, 2148 EVEX_W_0F2F_P_0, 2149 EVEX_W_0F2F_P_2, 2150 EVEX_W_0F51_P_0, 2151 EVEX_W_0F51_P_1, 2152 EVEX_W_0F51_P_2, 2153 EVEX_W_0F51_P_3, 2154 EVEX_W_0F54_P_0, 2155 EVEX_W_0F54_P_2, 2156 EVEX_W_0F55_P_0, 2157 EVEX_W_0F55_P_2, 2158 EVEX_W_0F56_P_0, 2159 EVEX_W_0F56_P_2, 2160 EVEX_W_0F57_P_0, 2161 EVEX_W_0F57_P_2, 2162 EVEX_W_0F58_P_0, 2163 EVEX_W_0F58_P_1, 2164 EVEX_W_0F58_P_2, 2165 EVEX_W_0F58_P_3, 2166 EVEX_W_0F59_P_0, 2167 EVEX_W_0F59_P_1, 2168 EVEX_W_0F59_P_2, 2169 EVEX_W_0F59_P_3, 2170 EVEX_W_0F5A_P_0, 2171 EVEX_W_0F5A_P_1, 2172 EVEX_W_0F5A_P_2, 2173 EVEX_W_0F5A_P_3, 2174 EVEX_W_0F5B_P_0, 2175 EVEX_W_0F5B_P_1, 2176 EVEX_W_0F5B_P_2, 2177 EVEX_W_0F5C_P_0, 2178 EVEX_W_0F5C_P_1, 2179 EVEX_W_0F5C_P_2, 2180 EVEX_W_0F5C_P_3, 2181 EVEX_W_0F5D_P_0, 2182 EVEX_W_0F5D_P_1, 2183 EVEX_W_0F5D_P_2, 2184 EVEX_W_0F5D_P_3, 2185 EVEX_W_0F5E_P_0, 2186 EVEX_W_0F5E_P_1, 2187 EVEX_W_0F5E_P_2, 2188 EVEX_W_0F5E_P_3, 2189 EVEX_W_0F5F_P_0, 2190 EVEX_W_0F5F_P_1, 2191 EVEX_W_0F5F_P_2, 2192 EVEX_W_0F5F_P_3, 2193 EVEX_W_0F62_P_2, 2194 EVEX_W_0F66_P_2, 2195 EVEX_W_0F6A_P_2, 2196 EVEX_W_0F6B_P_2, 2197 EVEX_W_0F6C_P_2, 2198 EVEX_W_0F6D_P_2, 2199 EVEX_W_0F6E_P_2, 2200 EVEX_W_0F6F_P_1, 2201 EVEX_W_0F6F_P_2, 2202 EVEX_W_0F6F_P_3, 2203 EVEX_W_0F70_P_2, 2204 EVEX_W_0F72_R_2_P_2, 2205 EVEX_W_0F72_R_6_P_2, 2206 EVEX_W_0F73_R_2_P_2, 2207 EVEX_W_0F73_R_6_P_2, 2208 EVEX_W_0F76_P_2, 2209 EVEX_W_0F78_P_0, 2210 EVEX_W_0F78_P_2, 2211 EVEX_W_0F79_P_0, 2212 EVEX_W_0F79_P_2, 2213 EVEX_W_0F7A_P_1, 2214 EVEX_W_0F7A_P_2, 2215 EVEX_W_0F7A_P_3, 2216 EVEX_W_0F7B_P_1, 2217 EVEX_W_0F7B_P_2, 2218 EVEX_W_0F7B_P_3, 2219 EVEX_W_0F7E_P_1, 2220 EVEX_W_0F7E_P_2, 2221 EVEX_W_0F7F_P_1, 2222 EVEX_W_0F7F_P_2, 2223 EVEX_W_0F7F_P_3, 2224 EVEX_W_0FC2_P_0, 2225 EVEX_W_0FC2_P_1, 2226 EVEX_W_0FC2_P_2, 2227 EVEX_W_0FC2_P_3, 2228 EVEX_W_0FC6_P_0, 2229 EVEX_W_0FC6_P_2, 2230 EVEX_W_0FD2_P_2, 2231 EVEX_W_0FD3_P_2, 2232 EVEX_W_0FD4_P_2, 2233 EVEX_W_0FD6_P_2, 2234 EVEX_W_0FE6_P_1, 2235 EVEX_W_0FE6_P_2, 2236 EVEX_W_0FE6_P_3, 2237 EVEX_W_0FE7_P_2, 2238 EVEX_W_0FF2_P_2, 2239 EVEX_W_0FF3_P_2, 2240 EVEX_W_0FF4_P_2, 2241 EVEX_W_0FFA_P_2, 2242 EVEX_W_0FFB_P_2, 2243 EVEX_W_0FFE_P_2, 2244 EVEX_W_0F380C_P_2, 2245 EVEX_W_0F380D_P_2, 2246 EVEX_W_0F3810_P_1, 2247 EVEX_W_0F3810_P_2, 2248 EVEX_W_0F3811_P_1, 2249 EVEX_W_0F3811_P_2, 2250 EVEX_W_0F3812_P_1, 2251 EVEX_W_0F3812_P_2, 2252 EVEX_W_0F3813_P_1, 2253 EVEX_W_0F3813_P_2, 2254 EVEX_W_0F3814_P_1, 2255 EVEX_W_0F3815_P_1, 2256 EVEX_W_0F3818_P_2, 2257 EVEX_W_0F3819_P_2, 2258 EVEX_W_0F381A_P_2, 2259 EVEX_W_0F381B_P_2, 2260 EVEX_W_0F381E_P_2, 2261 EVEX_W_0F381F_P_2, 2262 EVEX_W_0F3820_P_1, 2263 EVEX_W_0F3821_P_1, 2264 EVEX_W_0F3822_P_1, 2265 EVEX_W_0F3823_P_1, 2266 EVEX_W_0F3824_P_1, 2267 EVEX_W_0F3825_P_1, 2268 EVEX_W_0F3825_P_2, 2269 EVEX_W_0F3826_P_1, 2270 EVEX_W_0F3826_P_2, 2271 EVEX_W_0F3828_P_1, 2272 EVEX_W_0F3828_P_2, 2273 EVEX_W_0F3829_P_1, 2274 EVEX_W_0F3829_P_2, 2275 EVEX_W_0F382A_P_1, 2276 EVEX_W_0F382A_P_2, 2277 EVEX_W_0F382B_P_2, 2278 EVEX_W_0F3830_P_1, 2279 EVEX_W_0F3831_P_1, 2280 EVEX_W_0F3832_P_1, 2281 EVEX_W_0F3833_P_1, 2282 EVEX_W_0F3834_P_1, 2283 EVEX_W_0F3835_P_1, 2284 EVEX_W_0F3835_P_2, 2285 EVEX_W_0F3837_P_2, 2286 EVEX_W_0F3838_P_1, 2287 EVEX_W_0F3839_P_1, 2288 EVEX_W_0F383A_P_1, 2289 EVEX_W_0F3840_P_2, 2290 EVEX_W_0F3858_P_2, 2291 EVEX_W_0F3859_P_2, 2292 EVEX_W_0F385A_P_2, 2293 EVEX_W_0F385B_P_2, 2294 EVEX_W_0F3866_P_2, 2295 EVEX_W_0F3875_P_2, 2296 EVEX_W_0F3878_P_2, 2297 EVEX_W_0F3879_P_2, 2298 EVEX_W_0F387A_P_2, 2299 EVEX_W_0F387B_P_2, 2300 EVEX_W_0F387D_P_2, 2301 EVEX_W_0F3883_P_2, 2302 EVEX_W_0F388D_P_2, 2303 EVEX_W_0F3891_P_2, 2304 EVEX_W_0F3893_P_2, 2305 EVEX_W_0F38A1_P_2, 2306 EVEX_W_0F38A3_P_2, 2307 EVEX_W_0F38C7_R_1_P_2, 2308 EVEX_W_0F38C7_R_2_P_2, 2309 EVEX_W_0F38C7_R_5_P_2, 2310 EVEX_W_0F38C7_R_6_P_2, 2311 2312 EVEX_W_0F3A00_P_2, 2313 EVEX_W_0F3A01_P_2, 2314 EVEX_W_0F3A04_P_2, 2315 EVEX_W_0F3A05_P_2, 2316 EVEX_W_0F3A08_P_2, 2317 EVEX_W_0F3A09_P_2, 2318 EVEX_W_0F3A0A_P_2, 2319 EVEX_W_0F3A0B_P_2, 2320 EVEX_W_0F3A16_P_2, 2321 EVEX_W_0F3A18_P_2, 2322 EVEX_W_0F3A19_P_2, 2323 EVEX_W_0F3A1A_P_2, 2324 EVEX_W_0F3A1B_P_2, 2325 EVEX_W_0F3A1D_P_2, 2326 EVEX_W_0F3A21_P_2, 2327 EVEX_W_0F3A22_P_2, 2328 EVEX_W_0F3A23_P_2, 2329 EVEX_W_0F3A38_P_2, 2330 EVEX_W_0F3A39_P_2, 2331 EVEX_W_0F3A3A_P_2, 2332 EVEX_W_0F3A3B_P_2, 2333 EVEX_W_0F3A3E_P_2, 2334 EVEX_W_0F3A3F_P_2, 2335 EVEX_W_0F3A42_P_2, 2336 EVEX_W_0F3A43_P_2, 2337 EVEX_W_0F3A50_P_2, 2338 EVEX_W_0F3A51_P_2, 2339 EVEX_W_0F3A56_P_2, 2340 EVEX_W_0F3A57_P_2, 2341 EVEX_W_0F3A66_P_2, 2342 EVEX_W_0F3A67_P_2 2343 }; 2344 2345 typedef void (*op_rtn) (int bytemode, int sizeflag); 2346 2347 struct dis386 { 2348 const char *name; 2349 struct 2350 { 2351 op_rtn rtn; 2352 int bytemode; 2353 } op[MAX_OPERANDS]; 2354 }; 2355 2356 /* Upper case letters in the instruction names here are macros. 2357 'A' => print 'b' if no register operands or suffix_always is true 2358 'B' => print 'b' if suffix_always is true 2359 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 2360 size prefix 2361 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 2362 suffix_always is true 2363 'E' => print 'e' if 32-bit form of jcxz 2364 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 2365 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 2366 'H' => print ",pt" or ",pn" branch hint 2367 'I' => honor following macro letter even in Intel mode (implemented only 2368 for some of the macro letters) 2369 'J' => print 'l' 2370 'K' => print 'd' or 'q' if rex prefix is present. 2371 'L' => print 'l' if suffix_always is true 2372 'M' => print 'r' if intel_mnemonic is false. 2373 'N' => print 'n' if instruction has no wait "prefix" 2374 'O' => print 'd' or 'o' (or 'q' in Intel mode) 2375 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, 2376 or suffix_always is true. print 'q' if rex prefix is present. 2377 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always 2378 is true 2379 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 2380 'S' => print 'w', 'l' or 'q' if suffix_always is true 2381 'T' => print 'q' in 64bit mode and behave as 'P' otherwise 2382 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise 2383 'V' => print 'q' in 64bit mode and behave as 'S' otherwise 2384 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 2385 'X' => print 's', 'd' depending on data16 prefix (for XMM) 2386 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and 2387 suffix_always is true. 2388 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise 2389 '!' => change condition from true to false or from false to true. 2390 '%' => add 1 upper case letter to the macro. 2391 2392 2 upper case letter macros: 2393 "XY" => print 'x' or 'y' if no register operands or suffix_always 2394 is true. 2395 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) 2396 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand 2397 or suffix_always is true 2398 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise 2399 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise 2400 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise 2401 "LW" => print 'd', 'q' depending on the VEX.W bit 2402 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has 2403 an operand size prefix, or suffix_always is true. print 2404 'q' if rex prefix is present. 2405 2406 Many of the above letters print nothing in Intel mode. See "putop" 2407 for the details. 2408 2409 Braces '{' and '}', and vertical bars '|', indicate alternative 2410 mnemonic strings for AT&T and Intel. */ 2411 2412 static const struct dis386 dis386[] = { 2413 /* 00 */ 2414 { "addB", { Ebh1, Gb } }, 2415 { "addS", { Evh1, Gv } }, 2416 { "addB", { Gb, EbS } }, 2417 { "addS", { Gv, EvS } }, 2418 { "addB", { AL, Ib } }, 2419 { "addS", { eAX, Iv } }, 2420 { X86_64_TABLE (X86_64_06) }, 2421 { X86_64_TABLE (X86_64_07) }, 2422 /* 08 */ 2423 { "orB", { Ebh1, Gb } }, 2424 { "orS", { Evh1, Gv } }, 2425 { "orB", { Gb, EbS } }, 2426 { "orS", { Gv, EvS } }, 2427 { "orB", { AL, Ib } }, 2428 { "orS", { eAX, Iv } }, 2429 { X86_64_TABLE (X86_64_0D) }, 2430 { Bad_Opcode }, /* 0x0f extended opcode escape */ 2431 /* 10 */ 2432 { "adcB", { Ebh1, Gb } }, 2433 { "adcS", { Evh1, Gv } }, 2434 { "adcB", { Gb, EbS } }, 2435 { "adcS", { Gv, EvS } }, 2436 { "adcB", { AL, Ib } }, 2437 { "adcS", { eAX, Iv } }, 2438 { X86_64_TABLE (X86_64_16) }, 2439 { X86_64_TABLE (X86_64_17) }, 2440 /* 18 */ 2441 { "sbbB", { Ebh1, Gb } }, 2442 { "sbbS", { Evh1, Gv } }, 2443 { "sbbB", { Gb, EbS } }, 2444 { "sbbS", { Gv, EvS } }, 2445 { "sbbB", { AL, Ib } }, 2446 { "sbbS", { eAX, Iv } }, 2447 { X86_64_TABLE (X86_64_1E) }, 2448 { X86_64_TABLE (X86_64_1F) }, 2449 /* 20 */ 2450 { "andB", { Ebh1, Gb } }, 2451 { "andS", { Evh1, Gv } }, 2452 { "andB", { Gb, EbS } }, 2453 { "andS", { Gv, EvS } }, 2454 { "andB", { AL, Ib } }, 2455 { "andS", { eAX, Iv } }, 2456 { Bad_Opcode }, /* SEG ES prefix */ 2457 { X86_64_TABLE (X86_64_27) }, 2458 /* 28 */ 2459 { "subB", { Ebh1, Gb } }, 2460 { "subS", { Evh1, Gv } }, 2461 { "subB", { Gb, EbS } }, 2462 { "subS", { Gv, EvS } }, 2463 { "subB", { AL, Ib } }, 2464 { "subS", { eAX, Iv } }, 2465 { Bad_Opcode }, /* SEG CS prefix */ 2466 { X86_64_TABLE (X86_64_2F) }, 2467 /* 30 */ 2468 { "xorB", { Ebh1, Gb } }, 2469 { "xorS", { Evh1, Gv } }, 2470 { "xorB", { Gb, EbS } }, 2471 { "xorS", { Gv, EvS } }, 2472 { "xorB", { AL, Ib } }, 2473 { "xorS", { eAX, Iv } }, 2474 { Bad_Opcode }, /* SEG SS prefix */ 2475 { X86_64_TABLE (X86_64_37) }, 2476 /* 38 */ 2477 { "cmpB", { Eb, Gb } }, 2478 { "cmpS", { Ev, Gv } }, 2479 { "cmpB", { Gb, EbS } }, 2480 { "cmpS", { Gv, EvS } }, 2481 { "cmpB", { AL, Ib } }, 2482 { "cmpS", { eAX, Iv } }, 2483 { Bad_Opcode }, /* SEG DS prefix */ 2484 { X86_64_TABLE (X86_64_3F) }, 2485 /* 40 */ 2486 { "inc{S|}", { RMeAX } }, 2487 { "inc{S|}", { RMeCX } }, 2488 { "inc{S|}", { RMeDX } }, 2489 { "inc{S|}", { RMeBX } }, 2490 { "inc{S|}", { RMeSP } }, 2491 { "inc{S|}", { RMeBP } }, 2492 { "inc{S|}", { RMeSI } }, 2493 { "inc{S|}", { RMeDI } }, 2494 /* 48 */ 2495 { "dec{S|}", { RMeAX } }, 2496 { "dec{S|}", { RMeCX } }, 2497 { "dec{S|}", { RMeDX } }, 2498 { "dec{S|}", { RMeBX } }, 2499 { "dec{S|}", { RMeSP } }, 2500 { "dec{S|}", { RMeBP } }, 2501 { "dec{S|}", { RMeSI } }, 2502 { "dec{S|}", { RMeDI } }, 2503 /* 50 */ 2504 { "pushV", { RMrAX } }, 2505 { "pushV", { RMrCX } }, 2506 { "pushV", { RMrDX } }, 2507 { "pushV", { RMrBX } }, 2508 { "pushV", { RMrSP } }, 2509 { "pushV", { RMrBP } }, 2510 { "pushV", { RMrSI } }, 2511 { "pushV", { RMrDI } }, 2512 /* 58 */ 2513 { "popV", { RMrAX } }, 2514 { "popV", { RMrCX } }, 2515 { "popV", { RMrDX } }, 2516 { "popV", { RMrBX } }, 2517 { "popV", { RMrSP } }, 2518 { "popV", { RMrBP } }, 2519 { "popV", { RMrSI } }, 2520 { "popV", { RMrDI } }, 2521 /* 60 */ 2522 { X86_64_TABLE (X86_64_60) }, 2523 { X86_64_TABLE (X86_64_61) }, 2524 { X86_64_TABLE (X86_64_62) }, 2525 { X86_64_TABLE (X86_64_63) }, 2526 { Bad_Opcode }, /* seg fs */ 2527 { Bad_Opcode }, /* seg gs */ 2528 { Bad_Opcode }, /* op size prefix */ 2529 { Bad_Opcode }, /* adr size prefix */ 2530 /* 68 */ 2531 { "pushT", { sIv } }, 2532 { "imulS", { Gv, Ev, Iv } }, 2533 { "pushT", { sIbT } }, 2534 { "imulS", { Gv, Ev, sIb } }, 2535 { "ins{b|}", { Ybr, indirDX } }, 2536 { X86_64_TABLE (X86_64_6D) }, 2537 { "outs{b|}", { indirDXr, Xb } }, 2538 { X86_64_TABLE (X86_64_6F) }, 2539 /* 70 */ 2540 { "joH", { Jb, BND, cond_jump_flag } }, 2541 { "jnoH", { Jb, BND, cond_jump_flag } }, 2542 { "jbH", { Jb, BND, cond_jump_flag } }, 2543 { "jaeH", { Jb, BND, cond_jump_flag } }, 2544 { "jeH", { Jb, BND, cond_jump_flag } }, 2545 { "jneH", { Jb, BND, cond_jump_flag } }, 2546 { "jbeH", { Jb, BND, cond_jump_flag } }, 2547 { "jaH", { Jb, BND, cond_jump_flag } }, 2548 /* 78 */ 2549 { "jsH", { Jb, BND, cond_jump_flag } }, 2550 { "jnsH", { Jb, BND, cond_jump_flag } }, 2551 { "jpH", { Jb, BND, cond_jump_flag } }, 2552 { "jnpH", { Jb, BND, cond_jump_flag } }, 2553 { "jlH", { Jb, BND, cond_jump_flag } }, 2554 { "jgeH", { Jb, BND, cond_jump_flag } }, 2555 { "jleH", { Jb, BND, cond_jump_flag } }, 2556 { "jgH", { Jb, BND, cond_jump_flag } }, 2557 /* 80 */ 2558 { REG_TABLE (REG_80) }, 2559 { REG_TABLE (REG_81) }, 2560 { Bad_Opcode }, 2561 { REG_TABLE (REG_82) }, 2562 { "testB", { Eb, Gb } }, 2563 { "testS", { Ev, Gv } }, 2564 { "xchgB", { Ebh2, Gb } }, 2565 { "xchgS", { Evh2, Gv } }, 2566 /* 88 */ 2567 { "movB", { Ebh3, Gb } }, 2568 { "movS", { Evh3, Gv } }, 2569 { "movB", { Gb, EbS } }, 2570 { "movS", { Gv, EvS } }, 2571 { "movD", { Sv, Sw } }, 2572 { MOD_TABLE (MOD_8D) }, 2573 { "movD", { Sw, Sv } }, 2574 { REG_TABLE (REG_8F) }, 2575 /* 90 */ 2576 { PREFIX_TABLE (PREFIX_90) }, 2577 { "xchgS", { RMeCX, eAX } }, 2578 { "xchgS", { RMeDX, eAX } }, 2579 { "xchgS", { RMeBX, eAX } }, 2580 { "xchgS", { RMeSP, eAX } }, 2581 { "xchgS", { RMeBP, eAX } }, 2582 { "xchgS", { RMeSI, eAX } }, 2583 { "xchgS", { RMeDI, eAX } }, 2584 /* 98 */ 2585 { "cW{t|}R", { XX } }, 2586 { "cR{t|}O", { XX } }, 2587 { X86_64_TABLE (X86_64_9A) }, 2588 { Bad_Opcode }, /* fwait */ 2589 { "pushfT", { XX } }, 2590 { "popfT", { XX } }, 2591 { "sahf", { XX } }, 2592 { "lahf", { XX } }, 2593 /* a0 */ 2594 { "mov%LB", { AL, Ob } }, 2595 { "mov%LS", { eAX, Ov } }, 2596 { "mov%LB", { Ob, AL } }, 2597 { "mov%LS", { Ov, eAX } }, 2598 { "movs{b|}", { Ybr, Xb } }, 2599 { "movs{R|}", { Yvr, Xv } }, 2600 { "cmps{b|}", { Xb, Yb } }, 2601 { "cmps{R|}", { Xv, Yv } }, 2602 /* a8 */ 2603 { "testB", { AL, Ib } }, 2604 { "testS", { eAX, Iv } }, 2605 { "stosB", { Ybr, AL } }, 2606 { "stosS", { Yvr, eAX } }, 2607 { "lodsB", { ALr, Xb } }, 2608 { "lodsS", { eAXr, Xv } }, 2609 { "scasB", { AL, Yb } }, 2610 { "scasS", { eAX, Yv } }, 2611 /* b0 */ 2612 { "movB", { RMAL, Ib } }, 2613 { "movB", { RMCL, Ib } }, 2614 { "movB", { RMDL, Ib } }, 2615 { "movB", { RMBL, Ib } }, 2616 { "movB", { RMAH, Ib } }, 2617 { "movB", { RMCH, Ib } }, 2618 { "movB", { RMDH, Ib } }, 2619 { "movB", { RMBH, Ib } }, 2620 /* b8 */ 2621 { "mov%LV", { RMeAX, Iv64 } }, 2622 { "mov%LV", { RMeCX, Iv64 } }, 2623 { "mov%LV", { RMeDX, Iv64 } }, 2624 { "mov%LV", { RMeBX, Iv64 } }, 2625 { "mov%LV", { RMeSP, Iv64 } }, 2626 { "mov%LV", { RMeBP, Iv64 } }, 2627 { "mov%LV", { RMeSI, Iv64 } }, 2628 { "mov%LV", { RMeDI, Iv64 } }, 2629 /* c0 */ 2630 { REG_TABLE (REG_C0) }, 2631 { REG_TABLE (REG_C1) }, 2632 { "retT", { Iw, BND } }, 2633 { "retT", { BND } }, 2634 { X86_64_TABLE (X86_64_C4) }, 2635 { X86_64_TABLE (X86_64_C5) }, 2636 { REG_TABLE (REG_C6) }, 2637 { REG_TABLE (REG_C7) }, 2638 /* c8 */ 2639 { "enterT", { Iw, Ib } }, 2640 { "leaveT", { XX } }, 2641 { "Jret{|f}P", { Iw } }, 2642 { "Jret{|f}P", { XX } }, 2643 { "int3", { XX } }, 2644 { "int", { Ib } }, 2645 { X86_64_TABLE (X86_64_CE) }, 2646 { "iret%LP", { XX } }, 2647 /* d0 */ 2648 { REG_TABLE (REG_D0) }, 2649 { REG_TABLE (REG_D1) }, 2650 { REG_TABLE (REG_D2) }, 2651 { REG_TABLE (REG_D3) }, 2652 { X86_64_TABLE (X86_64_D4) }, 2653 { X86_64_TABLE (X86_64_D5) }, 2654 { Bad_Opcode }, 2655 { "xlat", { DSBX } }, 2656 /* d8 */ 2657 { FLOAT }, 2658 { FLOAT }, 2659 { FLOAT }, 2660 { FLOAT }, 2661 { FLOAT }, 2662 { FLOAT }, 2663 { FLOAT }, 2664 { FLOAT }, 2665 /* e0 */ 2666 { "loopneFH", { Jb, XX, loop_jcxz_flag } }, 2667 { "loopeFH", { Jb, XX, loop_jcxz_flag } }, 2668 { "loopFH", { Jb, XX, loop_jcxz_flag } }, 2669 { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, 2670 { "inB", { AL, Ib } }, 2671 { "inG", { zAX, Ib } }, 2672 { "outB", { Ib, AL } }, 2673 { "outG", { Ib, zAX } }, 2674 /* e8 */ 2675 { "callT", { Jv, BND } }, 2676 { "jmpT", { Jv, BND } }, 2677 { X86_64_TABLE (X86_64_EA) }, 2678 { "jmp", { Jb, BND } }, 2679 { "inB", { AL, indirDX } }, 2680 { "inG", { zAX, indirDX } }, 2681 { "outB", { indirDX, AL } }, 2682 { "outG", { indirDX, zAX } }, 2683 /* f0 */ 2684 { Bad_Opcode }, /* lock prefix */ 2685 { "icebp", { XX } }, 2686 { Bad_Opcode }, /* repne */ 2687 { Bad_Opcode }, /* repz */ 2688 { "hlt", { XX } }, 2689 { "cmc", { XX } }, 2690 { REG_TABLE (REG_F6) }, 2691 { REG_TABLE (REG_F7) }, 2692 /* f8 */ 2693 { "clc", { XX } }, 2694 { "stc", { XX } }, 2695 { "cli", { XX } }, 2696 { "sti", { XX } }, 2697 { "cld", { XX } }, 2698 { "std", { XX } }, 2699 { REG_TABLE (REG_FE) }, 2700 { REG_TABLE (REG_FF) }, 2701 }; 2702 2703 static const struct dis386 dis386_twobyte[] = { 2704 /* 00 */ 2705 { REG_TABLE (REG_0F00 ) }, 2706 { REG_TABLE (REG_0F01 ) }, 2707 { "larS", { Gv, Ew } }, 2708 { "lslS", { Gv, Ew } }, 2709 { Bad_Opcode }, 2710 { "syscall", { XX } }, 2711 { "clts", { XX } }, 2712 { "sysret%LP", { XX } }, 2713 /* 08 */ 2714 { "invd", { XX } }, 2715 { "wbinvd", { XX } }, 2716 { Bad_Opcode }, 2717 { "ud2", { XX } }, 2718 { Bad_Opcode }, 2719 { REG_TABLE (REG_0F0D) }, 2720 { "femms", { XX } }, 2721 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ 2722 /* 10 */ 2723 { PREFIX_TABLE (PREFIX_0F10) }, 2724 { PREFIX_TABLE (PREFIX_0F11) }, 2725 { PREFIX_TABLE (PREFIX_0F12) }, 2726 { MOD_TABLE (MOD_0F13) }, 2727 { "unpcklpX", { XM, EXx } }, 2728 { "unpckhpX", { XM, EXx } }, 2729 { PREFIX_TABLE (PREFIX_0F16) }, 2730 { MOD_TABLE (MOD_0F17) }, 2731 /* 18 */ 2732 { REG_TABLE (REG_0F18) }, 2733 { "nopQ", { Ev } }, 2734 { PREFIX_TABLE (PREFIX_0F1A) }, 2735 { PREFIX_TABLE (PREFIX_0F1B) }, 2736 { "nopQ", { Ev } }, 2737 { "nopQ", { Ev } }, 2738 { "nopQ", { Ev } }, 2739 { "nopQ", { Ev } }, 2740 /* 20 */ 2741 { "movZ", { Rm, Cm } }, 2742 { "movZ", { Rm, Dm } }, 2743 { "movZ", { Cm, Rm } }, 2744 { "movZ", { Dm, Rm } }, 2745 { MOD_TABLE (MOD_0F24) }, 2746 { Bad_Opcode }, 2747 { MOD_TABLE (MOD_0F26) }, 2748 { Bad_Opcode }, 2749 /* 28 */ 2750 { "movapX", { XM, EXx } }, 2751 { "movapX", { EXxS, XM } }, 2752 { PREFIX_TABLE (PREFIX_0F2A) }, 2753 { PREFIX_TABLE (PREFIX_0F2B) }, 2754 { PREFIX_TABLE (PREFIX_0F2C) }, 2755 { PREFIX_TABLE (PREFIX_0F2D) }, 2756 { PREFIX_TABLE (PREFIX_0F2E) }, 2757 { PREFIX_TABLE (PREFIX_0F2F) }, 2758 /* 30 */ 2759 { "wrmsr", { XX } }, 2760 { "rdtsc", { XX } }, 2761 { "rdmsr", { XX } }, 2762 { "rdpmc", { XX } }, 2763 { "sysenter", { XX } }, 2764 { "sysexit", { XX } }, 2765 { Bad_Opcode }, 2766 { "getsec", { XX } }, 2767 /* 38 */ 2768 { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, 2769 { Bad_Opcode }, 2770 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, 2771 { Bad_Opcode }, 2772 { Bad_Opcode }, 2773 { Bad_Opcode }, 2774 { Bad_Opcode }, 2775 { Bad_Opcode }, 2776 /* 40 */ 2777 { "cmovoS", { Gv, Ev } }, 2778 { "cmovnoS", { Gv, Ev } }, 2779 { "cmovbS", { Gv, Ev } }, 2780 { "cmovaeS", { Gv, Ev } }, 2781 { "cmoveS", { Gv, Ev } }, 2782 { "cmovneS", { Gv, Ev } }, 2783 { "cmovbeS", { Gv, Ev } }, 2784 { "cmovaS", { Gv, Ev } }, 2785 /* 48 */ 2786 { "cmovsS", { Gv, Ev } }, 2787 { "cmovnsS", { Gv, Ev } }, 2788 { "cmovpS", { Gv, Ev } }, 2789 { "cmovnpS", { Gv, Ev } }, 2790 { "cmovlS", { Gv, Ev } }, 2791 { "cmovgeS", { Gv, Ev } }, 2792 { "cmovleS", { Gv, Ev } }, 2793 { "cmovgS", { Gv, Ev } }, 2794 /* 50 */ 2795 { MOD_TABLE (MOD_0F51) }, 2796 { PREFIX_TABLE (PREFIX_0F51) }, 2797 { PREFIX_TABLE (PREFIX_0F52) }, 2798 { PREFIX_TABLE (PREFIX_0F53) }, 2799 { "andpX", { XM, EXx } }, 2800 { "andnpX", { XM, EXx } }, 2801 { "orpX", { XM, EXx } }, 2802 { "xorpX", { XM, EXx } }, 2803 /* 58 */ 2804 { PREFIX_TABLE (PREFIX_0F58) }, 2805 { PREFIX_TABLE (PREFIX_0F59) }, 2806 { PREFIX_TABLE (PREFIX_0F5A) }, 2807 { PREFIX_TABLE (PREFIX_0F5B) }, 2808 { PREFIX_TABLE (PREFIX_0F5C) }, 2809 { PREFIX_TABLE (PREFIX_0F5D) }, 2810 { PREFIX_TABLE (PREFIX_0F5E) }, 2811 { PREFIX_TABLE (PREFIX_0F5F) }, 2812 /* 60 */ 2813 { PREFIX_TABLE (PREFIX_0F60) }, 2814 { PREFIX_TABLE (PREFIX_0F61) }, 2815 { PREFIX_TABLE (PREFIX_0F62) }, 2816 { "packsswb", { MX, EM } }, 2817 { "pcmpgtb", { MX, EM } }, 2818 { "pcmpgtw", { MX, EM } }, 2819 { "pcmpgtd", { MX, EM } }, 2820 { "packuswb", { MX, EM } }, 2821 /* 68 */ 2822 { "punpckhbw", { MX, EM } }, 2823 { "punpckhwd", { MX, EM } }, 2824 { "punpckhdq", { MX, EM } }, 2825 { "packssdw", { MX, EM } }, 2826 { PREFIX_TABLE (PREFIX_0F6C) }, 2827 { PREFIX_TABLE (PREFIX_0F6D) }, 2828 { "movK", { MX, Edq } }, 2829 { PREFIX_TABLE (PREFIX_0F6F) }, 2830 /* 70 */ 2831 { PREFIX_TABLE (PREFIX_0F70) }, 2832 { REG_TABLE (REG_0F71) }, 2833 { REG_TABLE (REG_0F72) }, 2834 { REG_TABLE (REG_0F73) }, 2835 { "pcmpeqb", { MX, EM } }, 2836 { "pcmpeqw", { MX, EM } }, 2837 { "pcmpeqd", { MX, EM } }, 2838 { "emms", { XX } }, 2839 /* 78 */ 2840 { PREFIX_TABLE (PREFIX_0F78) }, 2841 { PREFIX_TABLE (PREFIX_0F79) }, 2842 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, 2843 { Bad_Opcode }, 2844 { PREFIX_TABLE (PREFIX_0F7C) }, 2845 { PREFIX_TABLE (PREFIX_0F7D) }, 2846 { PREFIX_TABLE (PREFIX_0F7E) }, 2847 { PREFIX_TABLE (PREFIX_0F7F) }, 2848 /* 80 */ 2849 { "joH", { Jv, BND, cond_jump_flag } }, 2850 { "jnoH", { Jv, BND, cond_jump_flag } }, 2851 { "jbH", { Jv, BND, cond_jump_flag } }, 2852 { "jaeH", { Jv, BND, cond_jump_flag } }, 2853 { "jeH", { Jv, BND, cond_jump_flag } }, 2854 { "jneH", { Jv, BND, cond_jump_flag } }, 2855 { "jbeH", { Jv, BND, cond_jump_flag } }, 2856 { "jaH", { Jv, BND, cond_jump_flag } }, 2857 /* 88 */ 2858 { "jsH", { Jv, BND, cond_jump_flag } }, 2859 { "jnsH", { Jv, BND, cond_jump_flag } }, 2860 { "jpH", { Jv, BND, cond_jump_flag } }, 2861 { "jnpH", { Jv, BND, cond_jump_flag } }, 2862 { "jlH", { Jv, BND, cond_jump_flag } }, 2863 { "jgeH", { Jv, BND, cond_jump_flag } }, 2864 { "jleH", { Jv, BND, cond_jump_flag } }, 2865 { "jgH", { Jv, BND, cond_jump_flag } }, 2866 /* 90 */ 2867 { "seto", { Eb } }, 2868 { "setno", { Eb } }, 2869 { "setb", { Eb } }, 2870 { "setae", { Eb } }, 2871 { "sete", { Eb } }, 2872 { "setne", { Eb } }, 2873 { "setbe", { Eb } }, 2874 { "seta", { Eb } }, 2875 /* 98 */ 2876 { "sets", { Eb } }, 2877 { "setns", { Eb } }, 2878 { "setp", { Eb } }, 2879 { "setnp", { Eb } }, 2880 { "setl", { Eb } }, 2881 { "setge", { Eb } }, 2882 { "setle", { Eb } }, 2883 { "setg", { Eb } }, 2884 /* a0 */ 2885 { "pushT", { fs } }, 2886 { "popT", { fs } }, 2887 { "cpuid", { XX } }, 2888 { "btS", { Ev, Gv } }, 2889 { "shldS", { Ev, Gv, Ib } }, 2890 { "shldS", { Ev, Gv, CL } }, 2891 { REG_TABLE (REG_0FA6) }, 2892 { REG_TABLE (REG_0FA7) }, 2893 /* a8 */ 2894 { "pushT", { gs } }, 2895 { "popT", { gs } }, 2896 { "rsm", { XX } }, 2897 { "btsS", { Evh1, Gv } }, 2898 { "shrdS", { Ev, Gv, Ib } }, 2899 { "shrdS", { Ev, Gv, CL } }, 2900 { REG_TABLE (REG_0FAE) }, 2901 { "imulS", { Gv, Ev } }, 2902 /* b0 */ 2903 { "cmpxchgB", { Ebh1, Gb } }, 2904 { "cmpxchgS", { Evh1, Gv } }, 2905 { MOD_TABLE (MOD_0FB2) }, 2906 { "btrS", { Evh1, Gv } }, 2907 { MOD_TABLE (MOD_0FB4) }, 2908 { MOD_TABLE (MOD_0FB5) }, 2909 { "movz{bR|x}", { Gv, Eb } }, 2910 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ 2911 /* b8 */ 2912 { PREFIX_TABLE (PREFIX_0FB8) }, 2913 { "ud1", { XX } }, 2914 { REG_TABLE (REG_0FBA) }, 2915 { "btcS", { Evh1, Gv } }, 2916 { PREFIX_TABLE (PREFIX_0FBC) }, 2917 { PREFIX_TABLE (PREFIX_0FBD) }, 2918 { "movs{bR|x}", { Gv, Eb } }, 2919 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ 2920 /* c0 */ 2921 { "xaddB", { Ebh1, Gb } }, 2922 { "xaddS", { Evh1, Gv } }, 2923 { PREFIX_TABLE (PREFIX_0FC2) }, 2924 { PREFIX_TABLE (PREFIX_0FC3) }, 2925 { "pinsrw", { MX, Edqw, Ib } }, 2926 { "pextrw", { Gdq, MS, Ib } }, 2927 { "shufpX", { XM, EXx, Ib } }, 2928 { REG_TABLE (REG_0FC7) }, 2929 /* c8 */ 2930 { "bswap", { RMeAX } }, 2931 { "bswap", { RMeCX } }, 2932 { "bswap", { RMeDX } }, 2933 { "bswap", { RMeBX } }, 2934 { "bswap", { RMeSP } }, 2935 { "bswap", { RMeBP } }, 2936 { "bswap", { RMeSI } }, 2937 { "bswap", { RMeDI } }, 2938 /* d0 */ 2939 { PREFIX_TABLE (PREFIX_0FD0) }, 2940 { "psrlw", { MX, EM } }, 2941 { "psrld", { MX, EM } }, 2942 { "psrlq", { MX, EM } }, 2943 { "paddq", { MX, EM } }, 2944 { "pmullw", { MX, EM } }, 2945 { PREFIX_TABLE (PREFIX_0FD6) }, 2946 { MOD_TABLE (MOD_0FD7) }, 2947 /* d8 */ 2948 { "psubusb", { MX, EM } }, 2949 { "psubusw", { MX, EM } }, 2950 { "pminub", { MX, EM } }, 2951 { "pand", { MX, EM } }, 2952 { "paddusb", { MX, EM } }, 2953 { "paddusw", { MX, EM } }, 2954 { "pmaxub", { MX, EM } }, 2955 { "pandn", { MX, EM } }, 2956 /* e0 */ 2957 { "pavgb", { MX, EM } }, 2958 { "psraw", { MX, EM } }, 2959 { "psrad", { MX, EM } }, 2960 { "pavgw", { MX, EM } }, 2961 { "pmulhuw", { MX, EM } }, 2962 { "pmulhw", { MX, EM } }, 2963 { PREFIX_TABLE (PREFIX_0FE6) }, 2964 { PREFIX_TABLE (PREFIX_0FE7) }, 2965 /* e8 */ 2966 { "psubsb", { MX, EM } }, 2967 { "psubsw", { MX, EM } }, 2968 { "pminsw", { MX, EM } }, 2969 { "por", { MX, EM } }, 2970 { "paddsb", { MX, EM } }, 2971 { "paddsw", { MX, EM } }, 2972 { "pmaxsw", { MX, EM } }, 2973 { "pxor", { MX, EM } }, 2974 /* f0 */ 2975 { PREFIX_TABLE (PREFIX_0FF0) }, 2976 { "psllw", { MX, EM } }, 2977 { "pslld", { MX, EM } }, 2978 { "psllq", { MX, EM } }, 2979 { "pmuludq", { MX, EM } }, 2980 { "pmaddwd", { MX, EM } }, 2981 { "psadbw", { MX, EM } }, 2982 { PREFIX_TABLE (PREFIX_0FF7) }, 2983 /* f8 */ 2984 { "psubb", { MX, EM } }, 2985 { "psubw", { MX, EM } }, 2986 { "psubd", { MX, EM } }, 2987 { "psubq", { MX, EM } }, 2988 { "paddb", { MX, EM } }, 2989 { "paddw", { MX, EM } }, 2990 { "paddd", { MX, EM } }, 2991 { Bad_Opcode }, 2992 }; 2993 2994 static const unsigned char onebyte_has_modrm[256] = { 2995 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2996 /* ------------------------------- */ 2997 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 2998 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 2999 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 3000 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 3001 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 3002 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 3003 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 3004 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 3005 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 3006 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 3007 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 3008 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 3009 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 3010 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 3011 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 3012 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 3013 /* ------------------------------- */ 3014 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3015 }; 3016 3017 static const unsigned char twobyte_has_modrm[256] = { 3018 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3019 /* ------------------------------- */ 3020 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 3021 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 3022 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 3023 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 3024 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 3025 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 3026 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 3027 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 3028 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 3029 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 3030 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 3031 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 3032 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 3033 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 3034 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 3035 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 3036 /* ------------------------------- */ 3037 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3038 }; 3039 3040 static const unsigned char twobyte_has_mandatory_prefix[256] = { 3041 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3042 /* ------------------------------- */ 3043 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ 3044 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */ 3045 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */ 3046 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 3047 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ 3048 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 3049 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 3050 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */ 3051 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 3052 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ 3053 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ 3054 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ 3055 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */ 3056 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 3057 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 3058 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 3059 /* ------------------------------- */ 3060 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 3061 }; 3062 3063 static char obuf[100]; 3064 static char *obufp; 3065 static char *mnemonicendp; 3066 static char scratchbuf[100]; 3067 static unsigned char *start_codep; 3068 static unsigned char *insn_codep; 3069 static unsigned char *codep; 3070 static unsigned char *end_codep; 3071 static int last_lock_prefix; 3072 static int last_repz_prefix; 3073 static int last_repnz_prefix; 3074 static int last_data_prefix; 3075 static int last_addr_prefix; 3076 static int last_rex_prefix; 3077 static int last_seg_prefix; 3078 static int fwait_prefix; 3079 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */ 3080 static int mandatory_prefix; 3081 /* The active segment register prefix. */ 3082 static int active_seg_prefix; 3083 #define MAX_CODE_LENGTH 15 3084 /* We can up to 14 prefixes since the maximum instruction length is 3085 15bytes. */ 3086 static int all_prefixes[MAX_CODE_LENGTH - 1]; 3087 static disassemble_info *the_info; 3088 static struct 3089 { 3090 int mod; 3091 int reg; 3092 int rm; 3093 } 3094 modrm; 3095 static unsigned char need_modrm; 3096 static struct 3097 { 3098 int scale; 3099 int index; 3100 int base; 3101 } 3102 sib; 3103 static struct 3104 { 3105 int register_specifier; 3106 int length; 3107 int prefix; 3108 int w; 3109 int evex; 3110 int r; 3111 int v; 3112 int mask_register_specifier; 3113 int zeroing; 3114 int ll; 3115 int b; 3116 } 3117 vex; 3118 static unsigned char need_vex; 3119 static unsigned char need_vex_reg; 3120 static unsigned char vex_w_done; 3121 3122 struct op 3123 { 3124 const char *name; 3125 unsigned int len; 3126 }; 3127 3128 /* If we are accessing mod/rm/reg without need_modrm set, then the 3129 values are stale. Hitting this abort likely indicates that you 3130 need to update onebyte_has_modrm or twobyte_has_modrm. */ 3131 #define MODRM_CHECK if (!need_modrm) abort () 3132 3133 static const char **names64; 3134 static const char **names32; 3135 static const char **names16; 3136 static const char **names8; 3137 static const char **names8rex; 3138 static const char **names_seg; 3139 static const char *index64; 3140 static const char *index32; 3141 static const char **index16; 3142 static const char **names_bnd; 3143 3144 static const char *intel_names64[] = { 3145 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 3146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3147 }; 3148 static const char *intel_names32[] = { 3149 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", 3150 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 3151 }; 3152 static const char *intel_names16[] = { 3153 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", 3154 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 3155 }; 3156 static const char *intel_names8[] = { 3157 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", 3158 }; 3159 static const char *intel_names8rex[] = { 3160 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", 3161 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" 3162 }; 3163 static const char *intel_names_seg[] = { 3164 "es", "cs", "ss", "ds", "fs", "gs", "?", "?", 3165 }; 3166 static const char *intel_index64 = "riz"; 3167 static const char *intel_index32 = "eiz"; 3168 static const char *intel_index16[] = { 3169 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 3170 }; 3171 3172 static const char *att_names64[] = { 3173 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 3174 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 3175 }; 3176 static const char *att_names32[] = { 3177 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 3178 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 3179 }; 3180 static const char *att_names16[] = { 3181 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 3182 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 3183 }; 3184 static const char *att_names8[] = { 3185 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 3186 }; 3187 static const char *att_names8rex[] = { 3188 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 3189 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 3190 }; 3191 static const char *att_names_seg[] = { 3192 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 3193 }; 3194 static const char *att_index64 = "%riz"; 3195 static const char *att_index32 = "%eiz"; 3196 static const char *att_index16[] = { 3197 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 3198 }; 3199 3200 static const char **names_mm; 3201 static const char *intel_names_mm[] = { 3202 "mm0", "mm1", "mm2", "mm3", 3203 "mm4", "mm5", "mm6", "mm7" 3204 }; 3205 static const char *att_names_mm[] = { 3206 "%mm0", "%mm1", "%mm2", "%mm3", 3207 "%mm4", "%mm5", "%mm6", "%mm7" 3208 }; 3209 3210 static const char *intel_names_bnd[] = { 3211 "bnd0", "bnd1", "bnd2", "bnd3" 3212 }; 3213 3214 static const char *att_names_bnd[] = { 3215 "%bnd0", "%bnd1", "%bnd2", "%bnd3" 3216 }; 3217 3218 static const char **names_xmm; 3219 static const char *intel_names_xmm[] = { 3220 "xmm0", "xmm1", "xmm2", "xmm3", 3221 "xmm4", "xmm5", "xmm6", "xmm7", 3222 "xmm8", "xmm9", "xmm10", "xmm11", 3223 "xmm12", "xmm13", "xmm14", "xmm15", 3224 "xmm16", "xmm17", "xmm18", "xmm19", 3225 "xmm20", "xmm21", "xmm22", "xmm23", 3226 "xmm24", "xmm25", "xmm26", "xmm27", 3227 "xmm28", "xmm29", "xmm30", "xmm31" 3228 }; 3229 static const char *att_names_xmm[] = { 3230 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 3231 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 3232 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 3233 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 3234 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 3235 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 3236 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 3237 "%xmm28", "%xmm29", "%xmm30", "%xmm31" 3238 }; 3239 3240 static const char **names_ymm; 3241 static const char *intel_names_ymm[] = { 3242 "ymm0", "ymm1", "ymm2", "ymm3", 3243 "ymm4", "ymm5", "ymm6", "ymm7", 3244 "ymm8", "ymm9", "ymm10", "ymm11", 3245 "ymm12", "ymm13", "ymm14", "ymm15", 3246 "ymm16", "ymm17", "ymm18", "ymm19", 3247 "ymm20", "ymm21", "ymm22", "ymm23", 3248 "ymm24", "ymm25", "ymm26", "ymm27", 3249 "ymm28", "ymm29", "ymm30", "ymm31" 3250 }; 3251 static const char *att_names_ymm[] = { 3252 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 3253 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 3254 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 3255 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 3256 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 3257 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 3258 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 3259 "%ymm28", "%ymm29", "%ymm30", "%ymm31" 3260 }; 3261 3262 static const char **names_zmm; 3263 static const char *intel_names_zmm[] = { 3264 "zmm0", "zmm1", "zmm2", "zmm3", 3265 "zmm4", "zmm5", "zmm6", "zmm7", 3266 "zmm8", "zmm9", "zmm10", "zmm11", 3267 "zmm12", "zmm13", "zmm14", "zmm15", 3268 "zmm16", "zmm17", "zmm18", "zmm19", 3269 "zmm20", "zmm21", "zmm22", "zmm23", 3270 "zmm24", "zmm25", "zmm26", "zmm27", 3271 "zmm28", "zmm29", "zmm30", "zmm31" 3272 }; 3273 static const char *att_names_zmm[] = { 3274 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 3275 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 3276 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 3277 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 3278 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 3279 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 3280 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 3281 "%zmm28", "%zmm29", "%zmm30", "%zmm31" 3282 }; 3283 3284 static const char **names_mask; 3285 static const char *intel_names_mask[] = { 3286 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" 3287 }; 3288 static const char *att_names_mask[] = { 3289 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 3290 }; 3291 3292 static const char *names_rounding[] = 3293 { 3294 "{rn-sae}", 3295 "{rd-sae}", 3296 "{ru-sae}", 3297 "{rz-sae}" 3298 }; 3299 3300 static const struct dis386 reg_table[][8] = { 3301 /* REG_80 */ 3302 { 3303 { "addA", { Ebh1, Ib } }, 3304 { "orA", { Ebh1, Ib } }, 3305 { "adcA", { Ebh1, Ib } }, 3306 { "sbbA", { Ebh1, Ib } }, 3307 { "andA", { Ebh1, Ib } }, 3308 { "subA", { Ebh1, Ib } }, 3309 { "xorA", { Ebh1, Ib } }, 3310 { "cmpA", { Eb, Ib } }, 3311 }, 3312 /* REG_81 */ 3313 { 3314 { "addQ", { Evh1, Iv } }, 3315 { "orQ", { Evh1, Iv } }, 3316 { "adcQ", { Evh1, Iv } }, 3317 { "sbbQ", { Evh1, Iv } }, 3318 { "andQ", { Evh1, Iv } }, 3319 { "subQ", { Evh1, Iv } }, 3320 { "xorQ", { Evh1, Iv } }, 3321 { "cmpQ", { Ev, Iv } }, 3322 }, 3323 /* REG_82 */ 3324 { 3325 { "addQ", { Evh1, sIb } }, 3326 { "orQ", { Evh1, sIb } }, 3327 { "adcQ", { Evh1, sIb } }, 3328 { "sbbQ", { Evh1, sIb } }, 3329 { "andQ", { Evh1, sIb } }, 3330 { "subQ", { Evh1, sIb } }, 3331 { "xorQ", { Evh1, sIb } }, 3332 { "cmpQ", { Ev, sIb } }, 3333 }, 3334 /* REG_8F */ 3335 { 3336 { "popU", { stackEv } }, 3337 { XOP_8F_TABLE (XOP_09) }, 3338 { Bad_Opcode }, 3339 { Bad_Opcode }, 3340 { Bad_Opcode }, 3341 { XOP_8F_TABLE (XOP_09) }, 3342 }, 3343 /* REG_C0 */ 3344 { 3345 { "rolA", { Eb, Ib } }, 3346 { "rorA", { Eb, Ib } }, 3347 { "rclA", { Eb, Ib } }, 3348 { "rcrA", { Eb, Ib } }, 3349 { "shlA", { Eb, Ib } }, 3350 { "shrA", { Eb, Ib } }, 3351 { Bad_Opcode }, 3352 { "sarA", { Eb, Ib } }, 3353 }, 3354 /* REG_C1 */ 3355 { 3356 { "rolQ", { Ev, Ib } }, 3357 { "rorQ", { Ev, Ib } }, 3358 { "rclQ", { Ev, Ib } }, 3359 { "rcrQ", { Ev, Ib } }, 3360 { "shlQ", { Ev, Ib } }, 3361 { "shrQ", { Ev, Ib } }, 3362 { Bad_Opcode }, 3363 { "sarQ", { Ev, Ib } }, 3364 }, 3365 /* REG_C6 */ 3366 { 3367 { "movA", { Ebh3, Ib } }, 3368 { Bad_Opcode }, 3369 { Bad_Opcode }, 3370 { Bad_Opcode }, 3371 { Bad_Opcode }, 3372 { Bad_Opcode }, 3373 { Bad_Opcode }, 3374 { MOD_TABLE (MOD_C6_REG_7) }, 3375 }, 3376 /* REG_C7 */ 3377 { 3378 { "movQ", { Evh3, Iv } }, 3379 { Bad_Opcode }, 3380 { Bad_Opcode }, 3381 { Bad_Opcode }, 3382 { Bad_Opcode }, 3383 { Bad_Opcode }, 3384 { Bad_Opcode }, 3385 { MOD_TABLE (MOD_C7_REG_7) }, 3386 }, 3387 /* REG_D0 */ 3388 { 3389 { "rolA", { Eb, I1 } }, 3390 { "rorA", { Eb, I1 } }, 3391 { "rclA", { Eb, I1 } }, 3392 { "rcrA", { Eb, I1 } }, 3393 { "shlA", { Eb, I1 } }, 3394 { "shrA", { Eb, I1 } }, 3395 { Bad_Opcode }, 3396 { "sarA", { Eb, I1 } }, 3397 }, 3398 /* REG_D1 */ 3399 { 3400 { "rolQ", { Ev, I1 } }, 3401 { "rorQ", { Ev, I1 } }, 3402 { "rclQ", { Ev, I1 } }, 3403 { "rcrQ", { Ev, I1 } }, 3404 { "shlQ", { Ev, I1 } }, 3405 { "shrQ", { Ev, I1 } }, 3406 { Bad_Opcode }, 3407 { "sarQ", { Ev, I1 } }, 3408 }, 3409 /* REG_D2 */ 3410 { 3411 { "rolA", { Eb, CL } }, 3412 { "rorA", { Eb, CL } }, 3413 { "rclA", { Eb, CL } }, 3414 { "rcrA", { Eb, CL } }, 3415 { "shlA", { Eb, CL } }, 3416 { "shrA", { Eb, CL } }, 3417 { Bad_Opcode }, 3418 { "sarA", { Eb, CL } }, 3419 }, 3420 /* REG_D3 */ 3421 { 3422 { "rolQ", { Ev, CL } }, 3423 { "rorQ", { Ev, CL } }, 3424 { "rclQ", { Ev, CL } }, 3425 { "rcrQ", { Ev, CL } }, 3426 { "shlQ", { Ev, CL } }, 3427 { "shrQ", { Ev, CL } }, 3428 { Bad_Opcode }, 3429 { "sarQ", { Ev, CL } }, 3430 }, 3431 /* REG_F6 */ 3432 { 3433 { "testA", { Eb, Ib } }, 3434 { Bad_Opcode }, 3435 { "notA", { Ebh1 } }, 3436 { "negA", { Ebh1 } }, 3437 { "mulA", { Eb } }, /* Don't print the implicit %al register, */ 3438 { "imulA", { Eb } }, /* to distinguish these opcodes from other */ 3439 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ 3440 { "idivA", { Eb } }, /* and idiv for consistency. */ 3441 }, 3442 /* REG_F7 */ 3443 { 3444 { "testQ", { Ev, Iv } }, 3445 { Bad_Opcode }, 3446 { "notQ", { Evh1 } }, 3447 { "negQ", { Evh1 } }, 3448 { "mulQ", { Ev } }, /* Don't print the implicit register. */ 3449 { "imulQ", { Ev } }, 3450 { "divQ", { Ev } }, 3451 { "idivQ", { Ev } }, 3452 }, 3453 /* REG_FE */ 3454 { 3455 { "incA", { Ebh1 } }, 3456 { "decA", { Ebh1 } }, 3457 }, 3458 /* REG_FF */ 3459 { 3460 { "incQ", { Evh1 } }, 3461 { "decQ", { Evh1 } }, 3462 { "call{T|}", { indirEv, BND } }, 3463 { MOD_TABLE (MOD_FF_REG_3) }, 3464 { "jmp{T|}", { indirEv, BND } }, 3465 { MOD_TABLE (MOD_FF_REG_5) }, 3466 { "pushU", { stackEv } }, 3467 { Bad_Opcode }, 3468 }, 3469 /* REG_0F00 */ 3470 { 3471 { "sldtD", { Sv } }, 3472 { "strD", { Sv } }, 3473 { "lldt", { Ew } }, 3474 { "ltr", { Ew } }, 3475 { "verr", { Ew } }, 3476 { "verw", { Ew } }, 3477 { Bad_Opcode }, 3478 { Bad_Opcode }, 3479 }, 3480 /* REG_0F01 */ 3481 { 3482 { MOD_TABLE (MOD_0F01_REG_0) }, 3483 { MOD_TABLE (MOD_0F01_REG_1) }, 3484 { MOD_TABLE (MOD_0F01_REG_2) }, 3485 { MOD_TABLE (MOD_0F01_REG_3) }, 3486 { "smswD", { Sv } }, 3487 { Bad_Opcode }, 3488 { "lmsw", { Ew } }, 3489 { MOD_TABLE (MOD_0F01_REG_7) }, 3490 }, 3491 /* REG_0F0D */ 3492 { 3493 { "prefetch", { Mb } }, 3494 { "prefetchw", { Mb } }, 3495 { "prefetchwt1", { Mb } }, 3496 { "prefetch", { Mb } }, 3497 { "prefetch", { Mb } }, 3498 { "prefetch", { Mb } }, 3499 { "prefetch", { Mb } }, 3500 { "prefetch", { Mb } }, 3501 }, 3502 /* REG_0F18 */ 3503 { 3504 { MOD_TABLE (MOD_0F18_REG_0) }, 3505 { MOD_TABLE (MOD_0F18_REG_1) }, 3506 { MOD_TABLE (MOD_0F18_REG_2) }, 3507 { MOD_TABLE (MOD_0F18_REG_3) }, 3508 { MOD_TABLE (MOD_0F18_REG_4) }, 3509 { MOD_TABLE (MOD_0F18_REG_5) }, 3510 { MOD_TABLE (MOD_0F18_REG_6) }, 3511 { MOD_TABLE (MOD_0F18_REG_7) }, 3512 }, 3513 /* REG_0F71 */ 3514 { 3515 { Bad_Opcode }, 3516 { Bad_Opcode }, 3517 { MOD_TABLE (MOD_0F71_REG_2) }, 3518 { Bad_Opcode }, 3519 { MOD_TABLE (MOD_0F71_REG_4) }, 3520 { Bad_Opcode }, 3521 { MOD_TABLE (MOD_0F71_REG_6) }, 3522 }, 3523 /* REG_0F72 */ 3524 { 3525 { Bad_Opcode }, 3526 { Bad_Opcode }, 3527 { MOD_TABLE (MOD_0F72_REG_2) }, 3528 { Bad_Opcode }, 3529 { MOD_TABLE (MOD_0F72_REG_4) }, 3530 { Bad_Opcode }, 3531 { MOD_TABLE (MOD_0F72_REG_6) }, 3532 }, 3533 /* REG_0F73 */ 3534 { 3535 { Bad_Opcode }, 3536 { Bad_Opcode }, 3537 { MOD_TABLE (MOD_0F73_REG_2) }, 3538 { MOD_TABLE (MOD_0F73_REG_3) }, 3539 { Bad_Opcode }, 3540 { Bad_Opcode }, 3541 { MOD_TABLE (MOD_0F73_REG_6) }, 3542 { MOD_TABLE (MOD_0F73_REG_7) }, 3543 }, 3544 /* REG_0FA6 */ 3545 { 3546 { "montmul", { { OP_0f07, 0 } } }, 3547 { "xsha1", { { OP_0f07, 0 } } }, 3548 { "xsha256", { { OP_0f07, 0 } } }, 3549 }, 3550 /* REG_0FA7 */ 3551 { 3552 { "xstore-rng", { { OP_0f07, 0 } } }, 3553 { "xcrypt-ecb", { { OP_0f07, 0 } } }, 3554 { "xcrypt-cbc", { { OP_0f07, 0 } } }, 3555 { "xcrypt-ctr", { { OP_0f07, 0 } } }, 3556 { "xcrypt-cfb", { { OP_0f07, 0 } } }, 3557 { "xcrypt-ofb", { { OP_0f07, 0 } } }, 3558 }, 3559 /* REG_0FAE */ 3560 { 3561 { MOD_TABLE (MOD_0FAE_REG_0) }, 3562 { MOD_TABLE (MOD_0FAE_REG_1) }, 3563 { MOD_TABLE (MOD_0FAE_REG_2) }, 3564 { MOD_TABLE (MOD_0FAE_REG_3) }, 3565 { MOD_TABLE (MOD_0FAE_REG_4) }, 3566 { MOD_TABLE (MOD_0FAE_REG_5) }, 3567 { MOD_TABLE (MOD_0FAE_REG_6) }, 3568 { MOD_TABLE (MOD_0FAE_REG_7) }, 3569 }, 3570 /* REG_0FBA */ 3571 { 3572 { Bad_Opcode }, 3573 { Bad_Opcode }, 3574 { Bad_Opcode }, 3575 { Bad_Opcode }, 3576 { "btQ", { Ev, Ib } }, 3577 { "btsQ", { Evh1, Ib } }, 3578 { "btrQ", { Evh1, Ib } }, 3579 { "btcQ", { Evh1, Ib } }, 3580 }, 3581 /* REG_0FC7 */ 3582 { 3583 { Bad_Opcode }, 3584 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, 3585 { Bad_Opcode }, 3586 { MOD_TABLE (MOD_0FC7_REG_3) }, 3587 { MOD_TABLE (MOD_0FC7_REG_4) }, 3588 { MOD_TABLE (MOD_0FC7_REG_5) }, 3589 { MOD_TABLE (MOD_0FC7_REG_6) }, 3590 { MOD_TABLE (MOD_0FC7_REG_7) }, 3591 }, 3592 /* REG_VEX_0F71 */ 3593 { 3594 { Bad_Opcode }, 3595 { Bad_Opcode }, 3596 { MOD_TABLE (MOD_VEX_0F71_REG_2) }, 3597 { Bad_Opcode }, 3598 { MOD_TABLE (MOD_VEX_0F71_REG_4) }, 3599 { Bad_Opcode }, 3600 { MOD_TABLE (MOD_VEX_0F71_REG_6) }, 3601 }, 3602 /* REG_VEX_0F72 */ 3603 { 3604 { Bad_Opcode }, 3605 { Bad_Opcode }, 3606 { MOD_TABLE (MOD_VEX_0F72_REG_2) }, 3607 { Bad_Opcode }, 3608 { MOD_TABLE (MOD_VEX_0F72_REG_4) }, 3609 { Bad_Opcode }, 3610 { MOD_TABLE (MOD_VEX_0F72_REG_6) }, 3611 }, 3612 /* REG_VEX_0F73 */ 3613 { 3614 { Bad_Opcode }, 3615 { Bad_Opcode }, 3616 { MOD_TABLE (MOD_VEX_0F73_REG_2) }, 3617 { MOD_TABLE (MOD_VEX_0F73_REG_3) }, 3618 { Bad_Opcode }, 3619 { Bad_Opcode }, 3620 { MOD_TABLE (MOD_VEX_0F73_REG_6) }, 3621 { MOD_TABLE (MOD_VEX_0F73_REG_7) }, 3622 }, 3623 /* REG_VEX_0FAE */ 3624 { 3625 { Bad_Opcode }, 3626 { Bad_Opcode }, 3627 { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, 3628 { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, 3629 }, 3630 /* REG_VEX_0F38F3 */ 3631 { 3632 { Bad_Opcode }, 3633 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, 3634 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, 3635 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, 3636 }, 3637 /* REG_XOP_LWPCB */ 3638 { 3639 { "llwpcb", { { OP_LWPCB_E, 0 } } }, 3640 { "slwpcb", { { OP_LWPCB_E, 0 } } }, 3641 }, 3642 /* REG_XOP_LWP */ 3643 { 3644 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, 3645 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, 3646 }, 3647 /* REG_XOP_TBM_01 */ 3648 { 3649 { Bad_Opcode }, 3650 { "blcfill", { { OP_LWP_E, 0 }, Ev } }, 3651 { "blsfill", { { OP_LWP_E, 0 }, Ev } }, 3652 { "blcs", { { OP_LWP_E, 0 }, Ev } }, 3653 { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, 3654 { "blcic", { { OP_LWP_E, 0 }, Ev } }, 3655 { "blsic", { { OP_LWP_E, 0 }, Ev } }, 3656 { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, 3657 }, 3658 /* REG_XOP_TBM_02 */ 3659 { 3660 { Bad_Opcode }, 3661 { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, 3662 { Bad_Opcode }, 3663 { Bad_Opcode }, 3664 { Bad_Opcode }, 3665 { Bad_Opcode }, 3666 { "blci", { { OP_LWP_E, 0 }, Ev } }, 3667 }, 3668 #define NEED_REG_TABLE 3669 #include "i386-dis-evex.h" 3670 #undef NEED_REG_TABLE 3671 }; 3672 3673 static const struct dis386 prefix_table[][4] = { 3674 /* PREFIX_90 */ 3675 { 3676 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 3677 { "pause", { XX } }, 3678 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 3679 }, 3680 3681 /* PREFIX_0F10 */ 3682 { 3683 { "movups", { XM, EXx } }, 3684 { "movss", { XM, EXd } }, 3685 { "movupd", { XM, EXx } }, 3686 { "movsd", { XM, EXq } }, 3687 }, 3688 3689 /* PREFIX_0F11 */ 3690 { 3691 { "movups", { EXxS, XM } }, 3692 { "movss", { EXdS, XM } }, 3693 { "movupd", { EXxS, XM } }, 3694 { "movsd", { EXqS, XM } }, 3695 }, 3696 3697 /* PREFIX_0F12 */ 3698 { 3699 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 3700 { "movsldup", { XM, EXx } }, 3701 { "movlpd", { XM, EXq } }, 3702 { "movddup", { XM, EXq } }, 3703 }, 3704 3705 /* PREFIX_0F16 */ 3706 { 3707 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 3708 { "movshdup", { XM, EXx } }, 3709 { "movhpd", { XM, EXq } }, 3710 }, 3711 3712 /* PREFIX_0F1A */ 3713 { 3714 { MOD_TABLE (MOD_0F1A_PREFIX_0) }, 3715 { "bndcl", { Gbnd, Ev_bnd } }, 3716 { "bndmov", { Gbnd, Ebnd } }, 3717 { "bndcu", { Gbnd, Ev_bnd } }, 3718 }, 3719 3720 /* PREFIX_0F1B */ 3721 { 3722 { MOD_TABLE (MOD_0F1B_PREFIX_0) }, 3723 { MOD_TABLE (MOD_0F1B_PREFIX_1) }, 3724 { "bndmov", { Ebnd, Gbnd } }, 3725 { "bndcn", { Gbnd, Ev_bnd } }, 3726 }, 3727 3728 /* PREFIX_0F2A */ 3729 { 3730 { "cvtpi2ps", { XM, EMCq } }, 3731 { "cvtsi2ss%LQ", { XM, Ev } }, 3732 { "cvtpi2pd", { XM, EMCq } }, 3733 { "cvtsi2sd%LQ", { XM, Ev } }, 3734 }, 3735 3736 /* PREFIX_0F2B */ 3737 { 3738 { MOD_TABLE (MOD_0F2B_PREFIX_0) }, 3739 { MOD_TABLE (MOD_0F2B_PREFIX_1) }, 3740 { MOD_TABLE (MOD_0F2B_PREFIX_2) }, 3741 { MOD_TABLE (MOD_0F2B_PREFIX_3) }, 3742 }, 3743 3744 /* PREFIX_0F2C */ 3745 { 3746 { "cvttps2pi", { MXC, EXq } }, 3747 { "cvttss2siY", { Gv, EXd } }, 3748 { "cvttpd2pi", { MXC, EXx } }, 3749 { "cvttsd2siY", { Gv, EXq } }, 3750 }, 3751 3752 /* PREFIX_0F2D */ 3753 { 3754 { "cvtps2pi", { MXC, EXq } }, 3755 { "cvtss2siY", { Gv, EXd } }, 3756 { "cvtpd2pi", { MXC, EXx } }, 3757 { "cvtsd2siY", { Gv, EXq } }, 3758 }, 3759 3760 /* PREFIX_0F2E */ 3761 { 3762 { "ucomiss",{ XM, EXd } }, 3763 { Bad_Opcode }, 3764 { "ucomisd",{ XM, EXq } }, 3765 }, 3766 3767 /* PREFIX_0F2F */ 3768 { 3769 { "comiss", { XM, EXd } }, 3770 { Bad_Opcode }, 3771 { "comisd", { XM, EXq } }, 3772 }, 3773 3774 /* PREFIX_0F51 */ 3775 { 3776 { "sqrtps", { XM, EXx } }, 3777 { "sqrtss", { XM, EXd } }, 3778 { "sqrtpd", { XM, EXx } }, 3779 { "sqrtsd", { XM, EXq } }, 3780 }, 3781 3782 /* PREFIX_0F52 */ 3783 { 3784 { "rsqrtps",{ XM, EXx } }, 3785 { "rsqrtss",{ XM, EXd } }, 3786 }, 3787 3788 /* PREFIX_0F53 */ 3789 { 3790 { "rcpps", { XM, EXx } }, 3791 { "rcpss", { XM, EXd } }, 3792 }, 3793 3794 /* PREFIX_0F58 */ 3795 { 3796 { "addps", { XM, EXx } }, 3797 { "addss", { XM, EXd } }, 3798 { "addpd", { XM, EXx } }, 3799 { "addsd", { XM, EXq } }, 3800 }, 3801 3802 /* PREFIX_0F59 */ 3803 { 3804 { "mulps", { XM, EXx } }, 3805 { "mulss", { XM, EXd } }, 3806 { "mulpd", { XM, EXx } }, 3807 { "mulsd", { XM, EXq } }, 3808 }, 3809 3810 /* PREFIX_0F5A */ 3811 { 3812 { "cvtps2pd", { XM, EXq } }, 3813 { "cvtss2sd", { XM, EXd } }, 3814 { "cvtpd2ps", { XM, EXx } }, 3815 { "cvtsd2ss", { XM, EXq } }, 3816 }, 3817 3818 /* PREFIX_0F5B */ 3819 { 3820 { "cvtdq2ps", { XM, EXx } }, 3821 { "cvttps2dq", { XM, EXx } }, 3822 { "cvtps2dq", { XM, EXx } }, 3823 }, 3824 3825 /* PREFIX_0F5C */ 3826 { 3827 { "subps", { XM, EXx } }, 3828 { "subss", { XM, EXd } }, 3829 { "subpd", { XM, EXx } }, 3830 { "subsd", { XM, EXq } }, 3831 }, 3832 3833 /* PREFIX_0F5D */ 3834 { 3835 { "minps", { XM, EXx } }, 3836 { "minss", { XM, EXd } }, 3837 { "minpd", { XM, EXx } }, 3838 { "minsd", { XM, EXq } }, 3839 }, 3840 3841 /* PREFIX_0F5E */ 3842 { 3843 { "divps", { XM, EXx } }, 3844 { "divss", { XM, EXd } }, 3845 { "divpd", { XM, EXx } }, 3846 { "divsd", { XM, EXq } }, 3847 }, 3848 3849 /* PREFIX_0F5F */ 3850 { 3851 { "maxps", { XM, EXx } }, 3852 { "maxss", { XM, EXd } }, 3853 { "maxpd", { XM, EXx } }, 3854 { "maxsd", { XM, EXq } }, 3855 }, 3856 3857 /* PREFIX_0F60 */ 3858 { 3859 { "punpcklbw",{ MX, EMd } }, 3860 { Bad_Opcode }, 3861 { "punpcklbw",{ MX, EMx } }, 3862 }, 3863 3864 /* PREFIX_0F61 */ 3865 { 3866 { "punpcklwd",{ MX, EMd } }, 3867 { Bad_Opcode }, 3868 { "punpcklwd",{ MX, EMx } }, 3869 }, 3870 3871 /* PREFIX_0F62 */ 3872 { 3873 { "punpckldq",{ MX, EMd } }, 3874 { Bad_Opcode }, 3875 { "punpckldq",{ MX, EMx } }, 3876 }, 3877 3878 /* PREFIX_0F6C */ 3879 { 3880 { Bad_Opcode }, 3881 { Bad_Opcode }, 3882 { "punpcklqdq", { XM, EXx } }, 3883 }, 3884 3885 /* PREFIX_0F6D */ 3886 { 3887 { Bad_Opcode }, 3888 { Bad_Opcode }, 3889 { "punpckhqdq", { XM, EXx } }, 3890 }, 3891 3892 /* PREFIX_0F6F */ 3893 { 3894 { "movq", { MX, EM } }, 3895 { "movdqu", { XM, EXx } }, 3896 { "movdqa", { XM, EXx } }, 3897 }, 3898 3899 /* PREFIX_0F70 */ 3900 { 3901 { "pshufw", { MX, EM, Ib } }, 3902 { "pshufhw",{ XM, EXx, Ib } }, 3903 { "pshufd", { XM, EXx, Ib } }, 3904 { "pshuflw",{ XM, EXx, Ib } }, 3905 }, 3906 3907 /* PREFIX_0F73_REG_3 */ 3908 { 3909 { Bad_Opcode }, 3910 { Bad_Opcode }, 3911 { "psrldq", { XS, Ib } }, 3912 }, 3913 3914 /* PREFIX_0F73_REG_7 */ 3915 { 3916 { Bad_Opcode }, 3917 { Bad_Opcode }, 3918 { "pslldq", { XS, Ib } }, 3919 }, 3920 3921 /* PREFIX_0F78 */ 3922 { 3923 {"vmread", { Em, Gm } }, 3924 { Bad_Opcode }, 3925 {"extrq", { XS, Ib, Ib } }, 3926 {"insertq", { XM, XS, Ib, Ib } }, 3927 }, 3928 3929 /* PREFIX_0F79 */ 3930 { 3931 {"vmwrite", { Gm, Em } }, 3932 { Bad_Opcode }, 3933 {"extrq", { XM, XS } }, 3934 {"insertq", { XM, XS } }, 3935 }, 3936 3937 /* PREFIX_0F7C */ 3938 { 3939 { Bad_Opcode }, 3940 { Bad_Opcode }, 3941 { "haddpd", { XM, EXx } }, 3942 { "haddps", { XM, EXx } }, 3943 }, 3944 3945 /* PREFIX_0F7D */ 3946 { 3947 { Bad_Opcode }, 3948 { Bad_Opcode }, 3949 { "hsubpd", { XM, EXx } }, 3950 { "hsubps", { XM, EXx } }, 3951 }, 3952 3953 /* PREFIX_0F7E */ 3954 { 3955 { "movK", { Edq, MX } }, 3956 { "movq", { XM, EXq } }, 3957 { "movK", { Edq, XM } }, 3958 }, 3959 3960 /* PREFIX_0F7F */ 3961 { 3962 { "movq", { EMS, MX } }, 3963 { "movdqu", { EXxS, XM } }, 3964 { "movdqa", { EXxS, XM } }, 3965 }, 3966 3967 /* PREFIX_0FAE_REG_0 */ 3968 { 3969 { Bad_Opcode }, 3970 { "rdfsbase", { Ev } }, 3971 }, 3972 3973 /* PREFIX_0FAE_REG_1 */ 3974 { 3975 { Bad_Opcode }, 3976 { "rdgsbase", { Ev } }, 3977 }, 3978 3979 /* PREFIX_0FAE_REG_2 */ 3980 { 3981 { Bad_Opcode }, 3982 { "wrfsbase", { Ev } }, 3983 }, 3984 3985 /* PREFIX_0FAE_REG_3 */ 3986 { 3987 { Bad_Opcode }, 3988 { "wrgsbase", { Ev } }, 3989 }, 3990 3991 /* PREFIX_0FAE_REG_6 */ 3992 { 3993 { "xsaveopt", { FXSAVE } }, 3994 { Bad_Opcode }, 3995 { "clwb", { Mb } }, 3996 }, 3997 3998 /* PREFIX_0FAE_REG_7 */ 3999 { 4000 { "clflush", { Mb } }, 4001 { Bad_Opcode }, 4002 { "clflushopt", { Mb } }, 4003 }, 4004 4005 /* PREFIX_RM_0_0FAE_REG_7 */ 4006 { 4007 { "sfence", { Skip_MODRM } }, 4008 { Bad_Opcode }, 4009 { "pcommit", { Skip_MODRM } }, 4010 }, 4011 4012 /* PREFIX_0FB8 */ 4013 { 4014 { Bad_Opcode }, 4015 { "popcntS", { Gv, Ev } }, 4016 }, 4017 4018 /* PREFIX_0FBC */ 4019 { 4020 { "bsfS", { Gv, Ev } }, 4021 { "tzcntS", { Gv, Ev } }, 4022 { "bsfS", { Gv, Ev } }, 4023 }, 4024 4025 /* PREFIX_0FBD */ 4026 { 4027 { "bsrS", { Gv, Ev } }, 4028 { "lzcntS", { Gv, Ev } }, 4029 { "bsrS", { Gv, Ev } }, 4030 }, 4031 4032 /* PREFIX_0FC2 */ 4033 { 4034 { "cmpps", { XM, EXx, CMP } }, 4035 { "cmpss", { XM, EXd, CMP } }, 4036 { "cmppd", { XM, EXx, CMP } }, 4037 { "cmpsd", { XM, EXq, CMP } }, 4038 }, 4039 4040 /* PREFIX_0FC3 */ 4041 { 4042 { "movntiS", { Ma, Gv } }, 4043 }, 4044 4045 /* PREFIX_0FC7_REG_6 */ 4046 { 4047 { "vmptrld",{ Mq } }, 4048 { "vmxon", { Mq } }, 4049 { "vmclear",{ Mq } }, 4050 }, 4051 4052 /* PREFIX_0FD0 */ 4053 { 4054 { Bad_Opcode }, 4055 { Bad_Opcode }, 4056 { "addsubpd", { XM, EXx } }, 4057 { "addsubps", { XM, EXx } }, 4058 }, 4059 4060 /* PREFIX_0FD6 */ 4061 { 4062 { Bad_Opcode }, 4063 { "movq2dq",{ XM, MS } }, 4064 { "movq", { EXqS, XM } }, 4065 { "movdq2q",{ MX, XS } }, 4066 }, 4067 4068 /* PREFIX_0FE6 */ 4069 { 4070 { Bad_Opcode }, 4071 { "cvtdq2pd", { XM, EXq } }, 4072 { "cvttpd2dq", { XM, EXx } }, 4073 { "cvtpd2dq", { XM, EXx } }, 4074 }, 4075 4076 /* PREFIX_0FE7 */ 4077 { 4078 { "movntq", { Mq, MX } }, 4079 { Bad_Opcode }, 4080 { MOD_TABLE (MOD_0FE7_PREFIX_2) }, 4081 }, 4082 4083 /* PREFIX_0FF0 */ 4084 { 4085 { Bad_Opcode }, 4086 { Bad_Opcode }, 4087 { Bad_Opcode }, 4088 { MOD_TABLE (MOD_0FF0_PREFIX_3) }, 4089 }, 4090 4091 /* PREFIX_0FF7 */ 4092 { 4093 { "maskmovq", { MX, MS } }, 4094 { Bad_Opcode }, 4095 { "maskmovdqu", { XM, XS } }, 4096 }, 4097 4098 /* PREFIX_0F3810 */ 4099 { 4100 { Bad_Opcode }, 4101 { Bad_Opcode }, 4102 { "pblendvb", { XM, EXx, XMM0 } }, 4103 }, 4104 4105 /* PREFIX_0F3814 */ 4106 { 4107 { Bad_Opcode }, 4108 { Bad_Opcode }, 4109 { "blendvps", { XM, EXx, XMM0 } }, 4110 }, 4111 4112 /* PREFIX_0F3815 */ 4113 { 4114 { Bad_Opcode }, 4115 { Bad_Opcode }, 4116 { "blendvpd", { XM, EXx, XMM0 } }, 4117 }, 4118 4119 /* PREFIX_0F3817 */ 4120 { 4121 { Bad_Opcode }, 4122 { Bad_Opcode }, 4123 { "ptest", { XM, EXx } }, 4124 }, 4125 4126 /* PREFIX_0F3820 */ 4127 { 4128 { Bad_Opcode }, 4129 { Bad_Opcode }, 4130 { "pmovsxbw", { XM, EXq } }, 4131 }, 4132 4133 /* PREFIX_0F3821 */ 4134 { 4135 { Bad_Opcode }, 4136 { Bad_Opcode }, 4137 { "pmovsxbd", { XM, EXd } }, 4138 }, 4139 4140 /* PREFIX_0F3822 */ 4141 { 4142 { Bad_Opcode }, 4143 { Bad_Opcode }, 4144 { "pmovsxbq", { XM, EXw } }, 4145 }, 4146 4147 /* PREFIX_0F3823 */ 4148 { 4149 { Bad_Opcode }, 4150 { Bad_Opcode }, 4151 { "pmovsxwd", { XM, EXq } }, 4152 }, 4153 4154 /* PREFIX_0F3824 */ 4155 { 4156 { Bad_Opcode }, 4157 { Bad_Opcode }, 4158 { "pmovsxwq", { XM, EXd } }, 4159 }, 4160 4161 /* PREFIX_0F3825 */ 4162 { 4163 { Bad_Opcode }, 4164 { Bad_Opcode }, 4165 { "pmovsxdq", { XM, EXq } }, 4166 }, 4167 4168 /* PREFIX_0F3828 */ 4169 { 4170 { Bad_Opcode }, 4171 { Bad_Opcode }, 4172 { "pmuldq", { XM, EXx } }, 4173 }, 4174 4175 /* PREFIX_0F3829 */ 4176 { 4177 { Bad_Opcode }, 4178 { Bad_Opcode }, 4179 { "pcmpeqq", { XM, EXx } }, 4180 }, 4181 4182 /* PREFIX_0F382A */ 4183 { 4184 { Bad_Opcode }, 4185 { Bad_Opcode }, 4186 { MOD_TABLE (MOD_0F382A_PREFIX_2) }, 4187 }, 4188 4189 /* PREFIX_0F382B */ 4190 { 4191 { Bad_Opcode }, 4192 { Bad_Opcode }, 4193 { "packusdw", { XM, EXx } }, 4194 }, 4195 4196 /* PREFIX_0F3830 */ 4197 { 4198 { Bad_Opcode }, 4199 { Bad_Opcode }, 4200 { "pmovzxbw", { XM, EXq } }, 4201 }, 4202 4203 /* PREFIX_0F3831 */ 4204 { 4205 { Bad_Opcode }, 4206 { Bad_Opcode }, 4207 { "pmovzxbd", { XM, EXd } }, 4208 }, 4209 4210 /* PREFIX_0F3832 */ 4211 { 4212 { Bad_Opcode }, 4213 { Bad_Opcode }, 4214 { "pmovzxbq", { XM, EXw } }, 4215 }, 4216 4217 /* PREFIX_0F3833 */ 4218 { 4219 { Bad_Opcode }, 4220 { Bad_Opcode }, 4221 { "pmovzxwd", { XM, EXq } }, 4222 }, 4223 4224 /* PREFIX_0F3834 */ 4225 { 4226 { Bad_Opcode }, 4227 { Bad_Opcode }, 4228 { "pmovzxwq", { XM, EXd } }, 4229 }, 4230 4231 /* PREFIX_0F3835 */ 4232 { 4233 { Bad_Opcode }, 4234 { Bad_Opcode }, 4235 { "pmovzxdq", { XM, EXq } }, 4236 }, 4237 4238 /* PREFIX_0F3837 */ 4239 { 4240 { Bad_Opcode }, 4241 { Bad_Opcode }, 4242 { "pcmpgtq", { XM, EXx } }, 4243 }, 4244 4245 /* PREFIX_0F3838 */ 4246 { 4247 { Bad_Opcode }, 4248 { Bad_Opcode }, 4249 { "pminsb", { XM, EXx } }, 4250 }, 4251 4252 /* PREFIX_0F3839 */ 4253 { 4254 { Bad_Opcode }, 4255 { Bad_Opcode }, 4256 { "pminsd", { XM, EXx } }, 4257 }, 4258 4259 /* PREFIX_0F383A */ 4260 { 4261 { Bad_Opcode }, 4262 { Bad_Opcode }, 4263 { "pminuw", { XM, EXx } }, 4264 }, 4265 4266 /* PREFIX_0F383B */ 4267 { 4268 { Bad_Opcode }, 4269 { Bad_Opcode }, 4270 { "pminud", { XM, EXx } }, 4271 }, 4272 4273 /* PREFIX_0F383C */ 4274 { 4275 { Bad_Opcode }, 4276 { Bad_Opcode }, 4277 { "pmaxsb", { XM, EXx } }, 4278 }, 4279 4280 /* PREFIX_0F383D */ 4281 { 4282 { Bad_Opcode }, 4283 { Bad_Opcode }, 4284 { "pmaxsd", { XM, EXx } }, 4285 }, 4286 4287 /* PREFIX_0F383E */ 4288 { 4289 { Bad_Opcode }, 4290 { Bad_Opcode }, 4291 { "pmaxuw", { XM, EXx } }, 4292 }, 4293 4294 /* PREFIX_0F383F */ 4295 { 4296 { Bad_Opcode }, 4297 { Bad_Opcode }, 4298 { "pmaxud", { XM, EXx } }, 4299 }, 4300 4301 /* PREFIX_0F3840 */ 4302 { 4303 { Bad_Opcode }, 4304 { Bad_Opcode }, 4305 { "pmulld", { XM, EXx } }, 4306 }, 4307 4308 /* PREFIX_0F3841 */ 4309 { 4310 { Bad_Opcode }, 4311 { Bad_Opcode }, 4312 { "phminposuw", { XM, EXx } }, 4313 }, 4314 4315 /* PREFIX_0F3880 */ 4316 { 4317 { Bad_Opcode }, 4318 { Bad_Opcode }, 4319 { "invept", { Gm, Mo } }, 4320 }, 4321 4322 /* PREFIX_0F3881 */ 4323 { 4324 { Bad_Opcode }, 4325 { Bad_Opcode }, 4326 { "invvpid", { Gm, Mo } }, 4327 }, 4328 4329 /* PREFIX_0F3882 */ 4330 { 4331 { Bad_Opcode }, 4332 { Bad_Opcode }, 4333 { "invpcid", { Gm, M } }, 4334 }, 4335 4336 /* PREFIX_0F38C8 */ 4337 { 4338 { "sha1nexte", { XM, EXxmm } }, 4339 }, 4340 4341 /* PREFIX_0F38C9 */ 4342 { 4343 { "sha1msg1", { XM, EXxmm } }, 4344 }, 4345 4346 /* PREFIX_0F38CA */ 4347 { 4348 { "sha1msg2", { XM, EXxmm } }, 4349 }, 4350 4351 /* PREFIX_0F38CB */ 4352 { 4353 { "sha256rnds2", { XM, EXxmm, XMM0 } }, 4354 }, 4355 4356 /* PREFIX_0F38CC */ 4357 { 4358 { "sha256msg1", { XM, EXxmm } }, 4359 }, 4360 4361 /* PREFIX_0F38CD */ 4362 { 4363 { "sha256msg2", { XM, EXxmm } }, 4364 }, 4365 4366 /* PREFIX_0F38DB */ 4367 { 4368 { Bad_Opcode }, 4369 { Bad_Opcode }, 4370 { "aesimc", { XM, EXx } }, 4371 }, 4372 4373 /* PREFIX_0F38DC */ 4374 { 4375 { Bad_Opcode }, 4376 { Bad_Opcode }, 4377 { "aesenc", { XM, EXx } }, 4378 }, 4379 4380 /* PREFIX_0F38DD */ 4381 { 4382 { Bad_Opcode }, 4383 { Bad_Opcode }, 4384 { "aesenclast", { XM, EXx } }, 4385 }, 4386 4387 /* PREFIX_0F38DE */ 4388 { 4389 { Bad_Opcode }, 4390 { Bad_Opcode }, 4391 { "aesdec", { XM, EXx } }, 4392 }, 4393 4394 /* PREFIX_0F38DF */ 4395 { 4396 { Bad_Opcode }, 4397 { Bad_Opcode }, 4398 { "aesdeclast", { XM, EXx } }, 4399 }, 4400 4401 /* PREFIX_0F38F0 */ 4402 { 4403 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 4404 { Bad_Opcode }, 4405 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 4406 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, 4407 }, 4408 4409 /* PREFIX_0F38F1 */ 4410 { 4411 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 4412 { Bad_Opcode }, 4413 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 4414 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, 4415 }, 4416 4417 /* PREFIX_0F38F6 */ 4418 { 4419 { Bad_Opcode }, 4420 { "adoxS", { Gdq, Edq} }, 4421 { "adcxS", { Gdq, Edq} }, 4422 { Bad_Opcode }, 4423 }, 4424 4425 /* PREFIX_0F3A08 */ 4426 { 4427 { Bad_Opcode }, 4428 { Bad_Opcode }, 4429 { "roundps", { XM, EXx, Ib } }, 4430 }, 4431 4432 /* PREFIX_0F3A09 */ 4433 { 4434 { Bad_Opcode }, 4435 { Bad_Opcode }, 4436 { "roundpd", { XM, EXx, Ib } }, 4437 }, 4438 4439 /* PREFIX_0F3A0A */ 4440 { 4441 { Bad_Opcode }, 4442 { Bad_Opcode }, 4443 { "roundss", { XM, EXd, Ib } }, 4444 }, 4445 4446 /* PREFIX_0F3A0B */ 4447 { 4448 { Bad_Opcode }, 4449 { Bad_Opcode }, 4450 { "roundsd", { XM, EXq, Ib } }, 4451 }, 4452 4453 /* PREFIX_0F3A0C */ 4454 { 4455 { Bad_Opcode }, 4456 { Bad_Opcode }, 4457 { "blendps", { XM, EXx, Ib } }, 4458 }, 4459 4460 /* PREFIX_0F3A0D */ 4461 { 4462 { Bad_Opcode }, 4463 { Bad_Opcode }, 4464 { "blendpd", { XM, EXx, Ib } }, 4465 }, 4466 4467 /* PREFIX_0F3A0E */ 4468 { 4469 { Bad_Opcode }, 4470 { Bad_Opcode }, 4471 { "pblendw", { XM, EXx, Ib } }, 4472 }, 4473 4474 /* PREFIX_0F3A14 */ 4475 { 4476 { Bad_Opcode }, 4477 { Bad_Opcode }, 4478 { "pextrb", { Edqb, XM, Ib } }, 4479 }, 4480 4481 /* PREFIX_0F3A15 */ 4482 { 4483 { Bad_Opcode }, 4484 { Bad_Opcode }, 4485 { "pextrw", { Edqw, XM, Ib } }, 4486 }, 4487 4488 /* PREFIX_0F3A16 */ 4489 { 4490 { Bad_Opcode }, 4491 { Bad_Opcode }, 4492 { "pextrK", { Edq, XM, Ib } }, 4493 }, 4494 4495 /* PREFIX_0F3A17 */ 4496 { 4497 { Bad_Opcode }, 4498 { Bad_Opcode }, 4499 { "extractps", { Edqd, XM, Ib } }, 4500 }, 4501 4502 /* PREFIX_0F3A20 */ 4503 { 4504 { Bad_Opcode }, 4505 { Bad_Opcode }, 4506 { "pinsrb", { XM, Edqb, Ib } }, 4507 }, 4508 4509 /* PREFIX_0F3A21 */ 4510 { 4511 { Bad_Opcode }, 4512 { Bad_Opcode }, 4513 { "insertps", { XM, EXd, Ib } }, 4514 }, 4515 4516 /* PREFIX_0F3A22 */ 4517 { 4518 { Bad_Opcode }, 4519 { Bad_Opcode }, 4520 { "pinsrK", { XM, Edq, Ib } }, 4521 }, 4522 4523 /* PREFIX_0F3A40 */ 4524 { 4525 { Bad_Opcode }, 4526 { Bad_Opcode }, 4527 { "dpps", { XM, EXx, Ib } }, 4528 }, 4529 4530 /* PREFIX_0F3A41 */ 4531 { 4532 { Bad_Opcode }, 4533 { Bad_Opcode }, 4534 { "dppd", { XM, EXx, Ib } }, 4535 }, 4536 4537 /* PREFIX_0F3A42 */ 4538 { 4539 { Bad_Opcode }, 4540 { Bad_Opcode }, 4541 { "mpsadbw", { XM, EXx, Ib } }, 4542 }, 4543 4544 /* PREFIX_0F3A44 */ 4545 { 4546 { Bad_Opcode }, 4547 { Bad_Opcode }, 4548 { "pclmulqdq", { XM, EXx, PCLMUL } }, 4549 }, 4550 4551 /* PREFIX_0F3A60 */ 4552 { 4553 { Bad_Opcode }, 4554 { Bad_Opcode }, 4555 { "pcmpestrm", { XM, EXx, Ib } }, 4556 }, 4557 4558 /* PREFIX_0F3A61 */ 4559 { 4560 { Bad_Opcode }, 4561 { Bad_Opcode }, 4562 { "pcmpestri", { XM, EXx, Ib } }, 4563 }, 4564 4565 /* PREFIX_0F3A62 */ 4566 { 4567 { Bad_Opcode }, 4568 { Bad_Opcode }, 4569 { "pcmpistrm", { XM, EXx, Ib } }, 4570 }, 4571 4572 /* PREFIX_0F3A63 */ 4573 { 4574 { Bad_Opcode }, 4575 { Bad_Opcode }, 4576 { "pcmpistri", { XM, EXx, Ib } }, 4577 }, 4578 4579 /* PREFIX_0F3ACC */ 4580 { 4581 { "sha1rnds4", { XM, EXxmm, Ib } }, 4582 }, 4583 4584 /* PREFIX_0F3ADF */ 4585 { 4586 { Bad_Opcode }, 4587 { Bad_Opcode }, 4588 { "aeskeygenassist", { XM, EXx, Ib } }, 4589 }, 4590 4591 /* PREFIX_VEX_0F10 */ 4592 { 4593 { VEX_W_TABLE (VEX_W_0F10_P_0) }, 4594 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, 4595 { VEX_W_TABLE (VEX_W_0F10_P_2) }, 4596 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, 4597 }, 4598 4599 /* PREFIX_VEX_0F11 */ 4600 { 4601 { VEX_W_TABLE (VEX_W_0F11_P_0) }, 4602 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, 4603 { VEX_W_TABLE (VEX_W_0F11_P_2) }, 4604 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, 4605 }, 4606 4607 /* PREFIX_VEX_0F12 */ 4608 { 4609 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, 4610 { VEX_W_TABLE (VEX_W_0F12_P_1) }, 4611 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, 4612 { VEX_W_TABLE (VEX_W_0F12_P_3) }, 4613 }, 4614 4615 /* PREFIX_VEX_0F16 */ 4616 { 4617 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, 4618 { VEX_W_TABLE (VEX_W_0F16_P_1) }, 4619 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, 4620 }, 4621 4622 /* PREFIX_VEX_0F2A */ 4623 { 4624 { Bad_Opcode }, 4625 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, 4626 { Bad_Opcode }, 4627 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, 4628 }, 4629 4630 /* PREFIX_VEX_0F2C */ 4631 { 4632 { Bad_Opcode }, 4633 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, 4634 { Bad_Opcode }, 4635 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, 4636 }, 4637 4638 /* PREFIX_VEX_0F2D */ 4639 { 4640 { Bad_Opcode }, 4641 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, 4642 { Bad_Opcode }, 4643 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, 4644 }, 4645 4646 /* PREFIX_VEX_0F2E */ 4647 { 4648 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, 4649 { Bad_Opcode }, 4650 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, 4651 }, 4652 4653 /* PREFIX_VEX_0F2F */ 4654 { 4655 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, 4656 { Bad_Opcode }, 4657 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, 4658 }, 4659 4660 /* PREFIX_VEX_0F41 */ 4661 { 4662 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, 4663 { Bad_Opcode }, 4664 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, 4665 }, 4666 4667 /* PREFIX_VEX_0F42 */ 4668 { 4669 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, 4670 { Bad_Opcode }, 4671 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, 4672 }, 4673 4674 /* PREFIX_VEX_0F44 */ 4675 { 4676 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, 4677 { Bad_Opcode }, 4678 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, 4679 }, 4680 4681 /* PREFIX_VEX_0F45 */ 4682 { 4683 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, 4684 { Bad_Opcode }, 4685 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, 4686 }, 4687 4688 /* PREFIX_VEX_0F46 */ 4689 { 4690 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, 4691 { Bad_Opcode }, 4692 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, 4693 }, 4694 4695 /* PREFIX_VEX_0F47 */ 4696 { 4697 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, 4698 { Bad_Opcode }, 4699 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, 4700 }, 4701 4702 /* PREFIX_VEX_0F4A */ 4703 { 4704 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, 4705 { Bad_Opcode }, 4706 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, 4707 }, 4708 4709 /* PREFIX_VEX_0F4B */ 4710 { 4711 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, 4712 { Bad_Opcode }, 4713 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, 4714 }, 4715 4716 /* PREFIX_VEX_0F51 */ 4717 { 4718 { VEX_W_TABLE (VEX_W_0F51_P_0) }, 4719 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, 4720 { VEX_W_TABLE (VEX_W_0F51_P_2) }, 4721 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, 4722 }, 4723 4724 /* PREFIX_VEX_0F52 */ 4725 { 4726 { VEX_W_TABLE (VEX_W_0F52_P_0) }, 4727 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, 4728 }, 4729 4730 /* PREFIX_VEX_0F53 */ 4731 { 4732 { VEX_W_TABLE (VEX_W_0F53_P_0) }, 4733 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, 4734 }, 4735 4736 /* PREFIX_VEX_0F58 */ 4737 { 4738 { VEX_W_TABLE (VEX_W_0F58_P_0) }, 4739 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, 4740 { VEX_W_TABLE (VEX_W_0F58_P_2) }, 4741 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, 4742 }, 4743 4744 /* PREFIX_VEX_0F59 */ 4745 { 4746 { VEX_W_TABLE (VEX_W_0F59_P_0) }, 4747 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, 4748 { VEX_W_TABLE (VEX_W_0F59_P_2) }, 4749 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, 4750 }, 4751 4752 /* PREFIX_VEX_0F5A */ 4753 { 4754 { VEX_W_TABLE (VEX_W_0F5A_P_0) }, 4755 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, 4756 { "vcvtpd2ps%XY", { XMM, EXx } }, 4757 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, 4758 }, 4759 4760 /* PREFIX_VEX_0F5B */ 4761 { 4762 { VEX_W_TABLE (VEX_W_0F5B_P_0) }, 4763 { VEX_W_TABLE (VEX_W_0F5B_P_1) }, 4764 { VEX_W_TABLE (VEX_W_0F5B_P_2) }, 4765 }, 4766 4767 /* PREFIX_VEX_0F5C */ 4768 { 4769 { VEX_W_TABLE (VEX_W_0F5C_P_0) }, 4770 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, 4771 { VEX_W_TABLE (VEX_W_0F5C_P_2) }, 4772 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, 4773 }, 4774 4775 /* PREFIX_VEX_0F5D */ 4776 { 4777 { VEX_W_TABLE (VEX_W_0F5D_P_0) }, 4778 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, 4779 { VEX_W_TABLE (VEX_W_0F5D_P_2) }, 4780 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, 4781 }, 4782 4783 /* PREFIX_VEX_0F5E */ 4784 { 4785 { VEX_W_TABLE (VEX_W_0F5E_P_0) }, 4786 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, 4787 { VEX_W_TABLE (VEX_W_0F5E_P_2) }, 4788 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, 4789 }, 4790 4791 /* PREFIX_VEX_0F5F */ 4792 { 4793 { VEX_W_TABLE (VEX_W_0F5F_P_0) }, 4794 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, 4795 { VEX_W_TABLE (VEX_W_0F5F_P_2) }, 4796 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, 4797 }, 4798 4799 /* PREFIX_VEX_0F60 */ 4800 { 4801 { Bad_Opcode }, 4802 { Bad_Opcode }, 4803 { VEX_W_TABLE (VEX_W_0F60_P_2) }, 4804 }, 4805 4806 /* PREFIX_VEX_0F61 */ 4807 { 4808 { Bad_Opcode }, 4809 { Bad_Opcode }, 4810 { VEX_W_TABLE (VEX_W_0F61_P_2) }, 4811 }, 4812 4813 /* PREFIX_VEX_0F62 */ 4814 { 4815 { Bad_Opcode }, 4816 { Bad_Opcode }, 4817 { VEX_W_TABLE (VEX_W_0F62_P_2) }, 4818 }, 4819 4820 /* PREFIX_VEX_0F63 */ 4821 { 4822 { Bad_Opcode }, 4823 { Bad_Opcode }, 4824 { VEX_W_TABLE (VEX_W_0F63_P_2) }, 4825 }, 4826 4827 /* PREFIX_VEX_0F64 */ 4828 { 4829 { Bad_Opcode }, 4830 { Bad_Opcode }, 4831 { VEX_W_TABLE (VEX_W_0F64_P_2) }, 4832 }, 4833 4834 /* PREFIX_VEX_0F65 */ 4835 { 4836 { Bad_Opcode }, 4837 { Bad_Opcode }, 4838 { VEX_W_TABLE (VEX_W_0F65_P_2) }, 4839 }, 4840 4841 /* PREFIX_VEX_0F66 */ 4842 { 4843 { Bad_Opcode }, 4844 { Bad_Opcode }, 4845 { VEX_W_TABLE (VEX_W_0F66_P_2) }, 4846 }, 4847 4848 /* PREFIX_VEX_0F67 */ 4849 { 4850 { Bad_Opcode }, 4851 { Bad_Opcode }, 4852 { VEX_W_TABLE (VEX_W_0F67_P_2) }, 4853 }, 4854 4855 /* PREFIX_VEX_0F68 */ 4856 { 4857 { Bad_Opcode }, 4858 { Bad_Opcode }, 4859 { VEX_W_TABLE (VEX_W_0F68_P_2) }, 4860 }, 4861 4862 /* PREFIX_VEX_0F69 */ 4863 { 4864 { Bad_Opcode }, 4865 { Bad_Opcode }, 4866 { VEX_W_TABLE (VEX_W_0F69_P_2) }, 4867 }, 4868 4869 /* PREFIX_VEX_0F6A */ 4870 { 4871 { Bad_Opcode }, 4872 { Bad_Opcode }, 4873 { VEX_W_TABLE (VEX_W_0F6A_P_2) }, 4874 }, 4875 4876 /* PREFIX_VEX_0F6B */ 4877 { 4878 { Bad_Opcode }, 4879 { Bad_Opcode }, 4880 { VEX_W_TABLE (VEX_W_0F6B_P_2) }, 4881 }, 4882 4883 /* PREFIX_VEX_0F6C */ 4884 { 4885 { Bad_Opcode }, 4886 { Bad_Opcode }, 4887 { VEX_W_TABLE (VEX_W_0F6C_P_2) }, 4888 }, 4889 4890 /* PREFIX_VEX_0F6D */ 4891 { 4892 { Bad_Opcode }, 4893 { Bad_Opcode }, 4894 { VEX_W_TABLE (VEX_W_0F6D_P_2) }, 4895 }, 4896 4897 /* PREFIX_VEX_0F6E */ 4898 { 4899 { Bad_Opcode }, 4900 { Bad_Opcode }, 4901 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, 4902 }, 4903 4904 /* PREFIX_VEX_0F6F */ 4905 { 4906 { Bad_Opcode }, 4907 { VEX_W_TABLE (VEX_W_0F6F_P_1) }, 4908 { VEX_W_TABLE (VEX_W_0F6F_P_2) }, 4909 }, 4910 4911 /* PREFIX_VEX_0F70 */ 4912 { 4913 { Bad_Opcode }, 4914 { VEX_W_TABLE (VEX_W_0F70_P_1) }, 4915 { VEX_W_TABLE (VEX_W_0F70_P_2) }, 4916 { VEX_W_TABLE (VEX_W_0F70_P_3) }, 4917 }, 4918 4919 /* PREFIX_VEX_0F71_REG_2 */ 4920 { 4921 { Bad_Opcode }, 4922 { Bad_Opcode }, 4923 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, 4924 }, 4925 4926 /* PREFIX_VEX_0F71_REG_4 */ 4927 { 4928 { Bad_Opcode }, 4929 { Bad_Opcode }, 4930 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, 4931 }, 4932 4933 /* PREFIX_VEX_0F71_REG_6 */ 4934 { 4935 { Bad_Opcode }, 4936 { Bad_Opcode }, 4937 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, 4938 }, 4939 4940 /* PREFIX_VEX_0F72_REG_2 */ 4941 { 4942 { Bad_Opcode }, 4943 { Bad_Opcode }, 4944 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, 4945 }, 4946 4947 /* PREFIX_VEX_0F72_REG_4 */ 4948 { 4949 { Bad_Opcode }, 4950 { Bad_Opcode }, 4951 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, 4952 }, 4953 4954 /* PREFIX_VEX_0F72_REG_6 */ 4955 { 4956 { Bad_Opcode }, 4957 { Bad_Opcode }, 4958 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, 4959 }, 4960 4961 /* PREFIX_VEX_0F73_REG_2 */ 4962 { 4963 { Bad_Opcode }, 4964 { Bad_Opcode }, 4965 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, 4966 }, 4967 4968 /* PREFIX_VEX_0F73_REG_3 */ 4969 { 4970 { Bad_Opcode }, 4971 { Bad_Opcode }, 4972 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, 4973 }, 4974 4975 /* PREFIX_VEX_0F73_REG_6 */ 4976 { 4977 { Bad_Opcode }, 4978 { Bad_Opcode }, 4979 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, 4980 }, 4981 4982 /* PREFIX_VEX_0F73_REG_7 */ 4983 { 4984 { Bad_Opcode }, 4985 { Bad_Opcode }, 4986 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, 4987 }, 4988 4989 /* PREFIX_VEX_0F74 */ 4990 { 4991 { Bad_Opcode }, 4992 { Bad_Opcode }, 4993 { VEX_W_TABLE (VEX_W_0F74_P_2) }, 4994 }, 4995 4996 /* PREFIX_VEX_0F75 */ 4997 { 4998 { Bad_Opcode }, 4999 { Bad_Opcode }, 5000 { VEX_W_TABLE (VEX_W_0F75_P_2) }, 5001 }, 5002 5003 /* PREFIX_VEX_0F76 */ 5004 { 5005 { Bad_Opcode }, 5006 { Bad_Opcode }, 5007 { VEX_W_TABLE (VEX_W_0F76_P_2) }, 5008 }, 5009 5010 /* PREFIX_VEX_0F77 */ 5011 { 5012 { VEX_W_TABLE (VEX_W_0F77_P_0) }, 5013 }, 5014 5015 /* PREFIX_VEX_0F7C */ 5016 { 5017 { Bad_Opcode }, 5018 { Bad_Opcode }, 5019 { VEX_W_TABLE (VEX_W_0F7C_P_2) }, 5020 { VEX_W_TABLE (VEX_W_0F7C_P_3) }, 5021 }, 5022 5023 /* PREFIX_VEX_0F7D */ 5024 { 5025 { Bad_Opcode }, 5026 { Bad_Opcode }, 5027 { VEX_W_TABLE (VEX_W_0F7D_P_2) }, 5028 { VEX_W_TABLE (VEX_W_0F7D_P_3) }, 5029 }, 5030 5031 /* PREFIX_VEX_0F7E */ 5032 { 5033 { Bad_Opcode }, 5034 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, 5035 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, 5036 }, 5037 5038 /* PREFIX_VEX_0F7F */ 5039 { 5040 { Bad_Opcode }, 5041 { VEX_W_TABLE (VEX_W_0F7F_P_1) }, 5042 { VEX_W_TABLE (VEX_W_0F7F_P_2) }, 5043 }, 5044 5045 /* PREFIX_VEX_0F90 */ 5046 { 5047 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, 5048 { Bad_Opcode }, 5049 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, 5050 }, 5051 5052 /* PREFIX_VEX_0F91 */ 5053 { 5054 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, 5055 { Bad_Opcode }, 5056 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, 5057 }, 5058 5059 /* PREFIX_VEX_0F92 */ 5060 { 5061 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, 5062 { Bad_Opcode }, 5063 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, 5064 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, 5065 }, 5066 5067 /* PREFIX_VEX_0F93 */ 5068 { 5069 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, 5070 { Bad_Opcode }, 5071 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, 5072 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, 5073 }, 5074 5075 /* PREFIX_VEX_0F98 */ 5076 { 5077 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, 5078 { Bad_Opcode }, 5079 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, 5080 }, 5081 5082 /* PREFIX_VEX_0F99 */ 5083 { 5084 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, 5085 { Bad_Opcode }, 5086 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, 5087 }, 5088 5089 /* PREFIX_VEX_0FC2 */ 5090 { 5091 { VEX_W_TABLE (VEX_W_0FC2_P_0) }, 5092 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, 5093 { VEX_W_TABLE (VEX_W_0FC2_P_2) }, 5094 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, 5095 }, 5096 5097 /* PREFIX_VEX_0FC4 */ 5098 { 5099 { Bad_Opcode }, 5100 { Bad_Opcode }, 5101 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, 5102 }, 5103 5104 /* PREFIX_VEX_0FC5 */ 5105 { 5106 { Bad_Opcode }, 5107 { Bad_Opcode }, 5108 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, 5109 }, 5110 5111 /* PREFIX_VEX_0FD0 */ 5112 { 5113 { Bad_Opcode }, 5114 { Bad_Opcode }, 5115 { VEX_W_TABLE (VEX_W_0FD0_P_2) }, 5116 { VEX_W_TABLE (VEX_W_0FD0_P_3) }, 5117 }, 5118 5119 /* PREFIX_VEX_0FD1 */ 5120 { 5121 { Bad_Opcode }, 5122 { Bad_Opcode }, 5123 { VEX_W_TABLE (VEX_W_0FD1_P_2) }, 5124 }, 5125 5126 /* PREFIX_VEX_0FD2 */ 5127 { 5128 { Bad_Opcode }, 5129 { Bad_Opcode }, 5130 { VEX_W_TABLE (VEX_W_0FD2_P_2) }, 5131 }, 5132 5133 /* PREFIX_VEX_0FD3 */ 5134 { 5135 { Bad_Opcode }, 5136 { Bad_Opcode }, 5137 { VEX_W_TABLE (VEX_W_0FD3_P_2) }, 5138 }, 5139 5140 /* PREFIX_VEX_0FD4 */ 5141 { 5142 { Bad_Opcode }, 5143 { Bad_Opcode }, 5144 { VEX_W_TABLE (VEX_W_0FD4_P_2) }, 5145 }, 5146 5147 /* PREFIX_VEX_0FD5 */ 5148 { 5149 { Bad_Opcode }, 5150 { Bad_Opcode }, 5151 { VEX_W_TABLE (VEX_W_0FD5_P_2) }, 5152 }, 5153 5154 /* PREFIX_VEX_0FD6 */ 5155 { 5156 { Bad_Opcode }, 5157 { Bad_Opcode }, 5158 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, 5159 }, 5160 5161 /* PREFIX_VEX_0FD7 */ 5162 { 5163 { Bad_Opcode }, 5164 { Bad_Opcode }, 5165 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, 5166 }, 5167 5168 /* PREFIX_VEX_0FD8 */ 5169 { 5170 { Bad_Opcode }, 5171 { Bad_Opcode }, 5172 { VEX_W_TABLE (VEX_W_0FD8_P_2) }, 5173 }, 5174 5175 /* PREFIX_VEX_0FD9 */ 5176 { 5177 { Bad_Opcode }, 5178 { Bad_Opcode }, 5179 { VEX_W_TABLE (VEX_W_0FD9_P_2) }, 5180 }, 5181 5182 /* PREFIX_VEX_0FDA */ 5183 { 5184 { Bad_Opcode }, 5185 { Bad_Opcode }, 5186 { VEX_W_TABLE (VEX_W_0FDA_P_2) }, 5187 }, 5188 5189 /* PREFIX_VEX_0FDB */ 5190 { 5191 { Bad_Opcode }, 5192 { Bad_Opcode }, 5193 { VEX_W_TABLE (VEX_W_0FDB_P_2) }, 5194 }, 5195 5196 /* PREFIX_VEX_0FDC */ 5197 { 5198 { Bad_Opcode }, 5199 { Bad_Opcode }, 5200 { VEX_W_TABLE (VEX_W_0FDC_P_2) }, 5201 }, 5202 5203 /* PREFIX_VEX_0FDD */ 5204 { 5205 { Bad_Opcode }, 5206 { Bad_Opcode }, 5207 { VEX_W_TABLE (VEX_W_0FDD_P_2) }, 5208 }, 5209 5210 /* PREFIX_VEX_0FDE */ 5211 { 5212 { Bad_Opcode }, 5213 { Bad_Opcode }, 5214 { VEX_W_TABLE (VEX_W_0FDE_P_2) }, 5215 }, 5216 5217 /* PREFIX_VEX_0FDF */ 5218 { 5219 { Bad_Opcode }, 5220 { Bad_Opcode }, 5221 { VEX_W_TABLE (VEX_W_0FDF_P_2) }, 5222 }, 5223 5224 /* PREFIX_VEX_0FE0 */ 5225 { 5226 { Bad_Opcode }, 5227 { Bad_Opcode }, 5228 { VEX_W_TABLE (VEX_W_0FE0_P_2) }, 5229 }, 5230 5231 /* PREFIX_VEX_0FE1 */ 5232 { 5233 { Bad_Opcode }, 5234 { Bad_Opcode }, 5235 { VEX_W_TABLE (VEX_W_0FE1_P_2) }, 5236 }, 5237 5238 /* PREFIX_VEX_0FE2 */ 5239 { 5240 { Bad_Opcode }, 5241 { Bad_Opcode }, 5242 { VEX_W_TABLE (VEX_W_0FE2_P_2) }, 5243 }, 5244 5245 /* PREFIX_VEX_0FE3 */ 5246 { 5247 { Bad_Opcode }, 5248 { Bad_Opcode }, 5249 { VEX_W_TABLE (VEX_W_0FE3_P_2) }, 5250 }, 5251 5252 /* PREFIX_VEX_0FE4 */ 5253 { 5254 { Bad_Opcode }, 5255 { Bad_Opcode }, 5256 { VEX_W_TABLE (VEX_W_0FE4_P_2) }, 5257 }, 5258 5259 /* PREFIX_VEX_0FE5 */ 5260 { 5261 { Bad_Opcode }, 5262 { Bad_Opcode }, 5263 { VEX_W_TABLE (VEX_W_0FE5_P_2) }, 5264 }, 5265 5266 /* PREFIX_VEX_0FE6 */ 5267 { 5268 { Bad_Opcode }, 5269 { VEX_W_TABLE (VEX_W_0FE6_P_1) }, 5270 { VEX_W_TABLE (VEX_W_0FE6_P_2) }, 5271 { VEX_W_TABLE (VEX_W_0FE6_P_3) }, 5272 }, 5273 5274 /* PREFIX_VEX_0FE7 */ 5275 { 5276 { Bad_Opcode }, 5277 { Bad_Opcode }, 5278 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, 5279 }, 5280 5281 /* PREFIX_VEX_0FE8 */ 5282 { 5283 { Bad_Opcode }, 5284 { Bad_Opcode }, 5285 { VEX_W_TABLE (VEX_W_0FE8_P_2) }, 5286 }, 5287 5288 /* PREFIX_VEX_0FE9 */ 5289 { 5290 { Bad_Opcode }, 5291 { Bad_Opcode }, 5292 { VEX_W_TABLE (VEX_W_0FE9_P_2) }, 5293 }, 5294 5295 /* PREFIX_VEX_0FEA */ 5296 { 5297 { Bad_Opcode }, 5298 { Bad_Opcode }, 5299 { VEX_W_TABLE (VEX_W_0FEA_P_2) }, 5300 }, 5301 5302 /* PREFIX_VEX_0FEB */ 5303 { 5304 { Bad_Opcode }, 5305 { Bad_Opcode }, 5306 { VEX_W_TABLE (VEX_W_0FEB_P_2) }, 5307 }, 5308 5309 /* PREFIX_VEX_0FEC */ 5310 { 5311 { Bad_Opcode }, 5312 { Bad_Opcode }, 5313 { VEX_W_TABLE (VEX_W_0FEC_P_2) }, 5314 }, 5315 5316 /* PREFIX_VEX_0FED */ 5317 { 5318 { Bad_Opcode }, 5319 { Bad_Opcode }, 5320 { VEX_W_TABLE (VEX_W_0FED_P_2) }, 5321 }, 5322 5323 /* PREFIX_VEX_0FEE */ 5324 { 5325 { Bad_Opcode }, 5326 { Bad_Opcode }, 5327 { VEX_W_TABLE (VEX_W_0FEE_P_2) }, 5328 }, 5329 5330 /* PREFIX_VEX_0FEF */ 5331 { 5332 { Bad_Opcode }, 5333 { Bad_Opcode }, 5334 { VEX_W_TABLE (VEX_W_0FEF_P_2) }, 5335 }, 5336 5337 /* PREFIX_VEX_0FF0 */ 5338 { 5339 { Bad_Opcode }, 5340 { Bad_Opcode }, 5341 { Bad_Opcode }, 5342 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, 5343 }, 5344 5345 /* PREFIX_VEX_0FF1 */ 5346 { 5347 { Bad_Opcode }, 5348 { Bad_Opcode }, 5349 { VEX_W_TABLE (VEX_W_0FF1_P_2) }, 5350 }, 5351 5352 /* PREFIX_VEX_0FF2 */ 5353 { 5354 { Bad_Opcode }, 5355 { Bad_Opcode }, 5356 { VEX_W_TABLE (VEX_W_0FF2_P_2) }, 5357 }, 5358 5359 /* PREFIX_VEX_0FF3 */ 5360 { 5361 { Bad_Opcode }, 5362 { Bad_Opcode }, 5363 { VEX_W_TABLE (VEX_W_0FF3_P_2) }, 5364 }, 5365 5366 /* PREFIX_VEX_0FF4 */ 5367 { 5368 { Bad_Opcode }, 5369 { Bad_Opcode }, 5370 { VEX_W_TABLE (VEX_W_0FF4_P_2) }, 5371 }, 5372 5373 /* PREFIX_VEX_0FF5 */ 5374 { 5375 { Bad_Opcode }, 5376 { Bad_Opcode }, 5377 { VEX_W_TABLE (VEX_W_0FF5_P_2) }, 5378 }, 5379 5380 /* PREFIX_VEX_0FF6 */ 5381 { 5382 { Bad_Opcode }, 5383 { Bad_Opcode }, 5384 { VEX_W_TABLE (VEX_W_0FF6_P_2) }, 5385 }, 5386 5387 /* PREFIX_VEX_0FF7 */ 5388 { 5389 { Bad_Opcode }, 5390 { Bad_Opcode }, 5391 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, 5392 }, 5393 5394 /* PREFIX_VEX_0FF8 */ 5395 { 5396 { Bad_Opcode }, 5397 { Bad_Opcode }, 5398 { VEX_W_TABLE (VEX_W_0FF8_P_2) }, 5399 }, 5400 5401 /* PREFIX_VEX_0FF9 */ 5402 { 5403 { Bad_Opcode }, 5404 { Bad_Opcode }, 5405 { VEX_W_TABLE (VEX_W_0FF9_P_2) }, 5406 }, 5407 5408 /* PREFIX_VEX_0FFA */ 5409 { 5410 { Bad_Opcode }, 5411 { Bad_Opcode }, 5412 { VEX_W_TABLE (VEX_W_0FFA_P_2) }, 5413 }, 5414 5415 /* PREFIX_VEX_0FFB */ 5416 { 5417 { Bad_Opcode }, 5418 { Bad_Opcode }, 5419 { VEX_W_TABLE (VEX_W_0FFB_P_2) }, 5420 }, 5421 5422 /* PREFIX_VEX_0FFC */ 5423 { 5424 { Bad_Opcode }, 5425 { Bad_Opcode }, 5426 { VEX_W_TABLE (VEX_W_0FFC_P_2) }, 5427 }, 5428 5429 /* PREFIX_VEX_0FFD */ 5430 { 5431 { Bad_Opcode }, 5432 { Bad_Opcode }, 5433 { VEX_W_TABLE (VEX_W_0FFD_P_2) }, 5434 }, 5435 5436 /* PREFIX_VEX_0FFE */ 5437 { 5438 { Bad_Opcode }, 5439 { Bad_Opcode }, 5440 { VEX_W_TABLE (VEX_W_0FFE_P_2) }, 5441 }, 5442 5443 /* PREFIX_VEX_0F3800 */ 5444 { 5445 { Bad_Opcode }, 5446 { Bad_Opcode }, 5447 { VEX_W_TABLE (VEX_W_0F3800_P_2) }, 5448 }, 5449 5450 /* PREFIX_VEX_0F3801 */ 5451 { 5452 { Bad_Opcode }, 5453 { Bad_Opcode }, 5454 { VEX_W_TABLE (VEX_W_0F3801_P_2) }, 5455 }, 5456 5457 /* PREFIX_VEX_0F3802 */ 5458 { 5459 { Bad_Opcode }, 5460 { Bad_Opcode }, 5461 { VEX_W_TABLE (VEX_W_0F3802_P_2) }, 5462 }, 5463 5464 /* PREFIX_VEX_0F3803 */ 5465 { 5466 { Bad_Opcode }, 5467 { Bad_Opcode }, 5468 { VEX_W_TABLE (VEX_W_0F3803_P_2) }, 5469 }, 5470 5471 /* PREFIX_VEX_0F3804 */ 5472 { 5473 { Bad_Opcode }, 5474 { Bad_Opcode }, 5475 { VEX_W_TABLE (VEX_W_0F3804_P_2) }, 5476 }, 5477 5478 /* PREFIX_VEX_0F3805 */ 5479 { 5480 { Bad_Opcode }, 5481 { Bad_Opcode }, 5482 { VEX_W_TABLE (VEX_W_0F3805_P_2) }, 5483 }, 5484 5485 /* PREFIX_VEX_0F3806 */ 5486 { 5487 { Bad_Opcode }, 5488 { Bad_Opcode }, 5489 { VEX_W_TABLE (VEX_W_0F3806_P_2) }, 5490 }, 5491 5492 /* PREFIX_VEX_0F3807 */ 5493 { 5494 { Bad_Opcode }, 5495 { Bad_Opcode }, 5496 { VEX_W_TABLE (VEX_W_0F3807_P_2) }, 5497 }, 5498 5499 /* PREFIX_VEX_0F3808 */ 5500 { 5501 { Bad_Opcode }, 5502 { Bad_Opcode }, 5503 { VEX_W_TABLE (VEX_W_0F3808_P_2) }, 5504 }, 5505 5506 /* PREFIX_VEX_0F3809 */ 5507 { 5508 { Bad_Opcode }, 5509 { Bad_Opcode }, 5510 { VEX_W_TABLE (VEX_W_0F3809_P_2) }, 5511 }, 5512 5513 /* PREFIX_VEX_0F380A */ 5514 { 5515 { Bad_Opcode }, 5516 { Bad_Opcode }, 5517 { VEX_W_TABLE (VEX_W_0F380A_P_2) }, 5518 }, 5519 5520 /* PREFIX_VEX_0F380B */ 5521 { 5522 { Bad_Opcode }, 5523 { Bad_Opcode }, 5524 { VEX_W_TABLE (VEX_W_0F380B_P_2) }, 5525 }, 5526 5527 /* PREFIX_VEX_0F380C */ 5528 { 5529 { Bad_Opcode }, 5530 { Bad_Opcode }, 5531 { VEX_W_TABLE (VEX_W_0F380C_P_2) }, 5532 }, 5533 5534 /* PREFIX_VEX_0F380D */ 5535 { 5536 { Bad_Opcode }, 5537 { Bad_Opcode }, 5538 { VEX_W_TABLE (VEX_W_0F380D_P_2) }, 5539 }, 5540 5541 /* PREFIX_VEX_0F380E */ 5542 { 5543 { Bad_Opcode }, 5544 { Bad_Opcode }, 5545 { VEX_W_TABLE (VEX_W_0F380E_P_2) }, 5546 }, 5547 5548 /* PREFIX_VEX_0F380F */ 5549 { 5550 { Bad_Opcode }, 5551 { Bad_Opcode }, 5552 { VEX_W_TABLE (VEX_W_0F380F_P_2) }, 5553 }, 5554 5555 /* PREFIX_VEX_0F3813 */ 5556 { 5557 { Bad_Opcode }, 5558 { Bad_Opcode }, 5559 { "vcvtph2ps", { XM, EXxmmq } }, 5560 }, 5561 5562 /* PREFIX_VEX_0F3816 */ 5563 { 5564 { Bad_Opcode }, 5565 { Bad_Opcode }, 5566 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, 5567 }, 5568 5569 /* PREFIX_VEX_0F3817 */ 5570 { 5571 { Bad_Opcode }, 5572 { Bad_Opcode }, 5573 { VEX_W_TABLE (VEX_W_0F3817_P_2) }, 5574 }, 5575 5576 /* PREFIX_VEX_0F3818 */ 5577 { 5578 { Bad_Opcode }, 5579 { Bad_Opcode }, 5580 { VEX_W_TABLE (VEX_W_0F3818_P_2) }, 5581 }, 5582 5583 /* PREFIX_VEX_0F3819 */ 5584 { 5585 { Bad_Opcode }, 5586 { Bad_Opcode }, 5587 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, 5588 }, 5589 5590 /* PREFIX_VEX_0F381A */ 5591 { 5592 { Bad_Opcode }, 5593 { Bad_Opcode }, 5594 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, 5595 }, 5596 5597 /* PREFIX_VEX_0F381C */ 5598 { 5599 { Bad_Opcode }, 5600 { Bad_Opcode }, 5601 { VEX_W_TABLE (VEX_W_0F381C_P_2) }, 5602 }, 5603 5604 /* PREFIX_VEX_0F381D */ 5605 { 5606 { Bad_Opcode }, 5607 { Bad_Opcode }, 5608 { VEX_W_TABLE (VEX_W_0F381D_P_2) }, 5609 }, 5610 5611 /* PREFIX_VEX_0F381E */ 5612 { 5613 { Bad_Opcode }, 5614 { Bad_Opcode }, 5615 { VEX_W_TABLE (VEX_W_0F381E_P_2) }, 5616 }, 5617 5618 /* PREFIX_VEX_0F3820 */ 5619 { 5620 { Bad_Opcode }, 5621 { Bad_Opcode }, 5622 { VEX_W_TABLE (VEX_W_0F3820_P_2) }, 5623 }, 5624 5625 /* PREFIX_VEX_0F3821 */ 5626 { 5627 { Bad_Opcode }, 5628 { Bad_Opcode }, 5629 { VEX_W_TABLE (VEX_W_0F3821_P_2) }, 5630 }, 5631 5632 /* PREFIX_VEX_0F3822 */ 5633 { 5634 { Bad_Opcode }, 5635 { Bad_Opcode }, 5636 { VEX_W_TABLE (VEX_W_0F3822_P_2) }, 5637 }, 5638 5639 /* PREFIX_VEX_0F3823 */ 5640 { 5641 { Bad_Opcode }, 5642 { Bad_Opcode }, 5643 { VEX_W_TABLE (VEX_W_0F3823_P_2) }, 5644 }, 5645 5646 /* PREFIX_VEX_0F3824 */ 5647 { 5648 { Bad_Opcode }, 5649 { Bad_Opcode }, 5650 { VEX_W_TABLE (VEX_W_0F3824_P_2) }, 5651 }, 5652 5653 /* PREFIX_VEX_0F3825 */ 5654 { 5655 { Bad_Opcode }, 5656 { Bad_Opcode }, 5657 { VEX_W_TABLE (VEX_W_0F3825_P_2) }, 5658 }, 5659 5660 /* PREFIX_VEX_0F3828 */ 5661 { 5662 { Bad_Opcode }, 5663 { Bad_Opcode }, 5664 { VEX_W_TABLE (VEX_W_0F3828_P_2) }, 5665 }, 5666 5667 /* PREFIX_VEX_0F3829 */ 5668 { 5669 { Bad_Opcode }, 5670 { Bad_Opcode }, 5671 { VEX_W_TABLE (VEX_W_0F3829_P_2) }, 5672 }, 5673 5674 /* PREFIX_VEX_0F382A */ 5675 { 5676 { Bad_Opcode }, 5677 { Bad_Opcode }, 5678 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, 5679 }, 5680 5681 /* PREFIX_VEX_0F382B */ 5682 { 5683 { Bad_Opcode }, 5684 { Bad_Opcode }, 5685 { VEX_W_TABLE (VEX_W_0F382B_P_2) }, 5686 }, 5687 5688 /* PREFIX_VEX_0F382C */ 5689 { 5690 { Bad_Opcode }, 5691 { Bad_Opcode }, 5692 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, 5693 }, 5694 5695 /* PREFIX_VEX_0F382D */ 5696 { 5697 { Bad_Opcode }, 5698 { Bad_Opcode }, 5699 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, 5700 }, 5701 5702 /* PREFIX_VEX_0F382E */ 5703 { 5704 { Bad_Opcode }, 5705 { Bad_Opcode }, 5706 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, 5707 }, 5708 5709 /* PREFIX_VEX_0F382F */ 5710 { 5711 { Bad_Opcode }, 5712 { Bad_Opcode }, 5713 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, 5714 }, 5715 5716 /* PREFIX_VEX_0F3830 */ 5717 { 5718 { Bad_Opcode }, 5719 { Bad_Opcode }, 5720 { VEX_W_TABLE (VEX_W_0F3830_P_2) }, 5721 }, 5722 5723 /* PREFIX_VEX_0F3831 */ 5724 { 5725 { Bad_Opcode }, 5726 { Bad_Opcode }, 5727 { VEX_W_TABLE (VEX_W_0F3831_P_2) }, 5728 }, 5729 5730 /* PREFIX_VEX_0F3832 */ 5731 { 5732 { Bad_Opcode }, 5733 { Bad_Opcode }, 5734 { VEX_W_TABLE (VEX_W_0F3832_P_2) }, 5735 }, 5736 5737 /* PREFIX_VEX_0F3833 */ 5738 { 5739 { Bad_Opcode }, 5740 { Bad_Opcode }, 5741 { VEX_W_TABLE (VEX_W_0F3833_P_2) }, 5742 }, 5743 5744 /* PREFIX_VEX_0F3834 */ 5745 { 5746 { Bad_Opcode }, 5747 { Bad_Opcode }, 5748 { VEX_W_TABLE (VEX_W_0F3834_P_2) }, 5749 }, 5750 5751 /* PREFIX_VEX_0F3835 */ 5752 { 5753 { Bad_Opcode }, 5754 { Bad_Opcode }, 5755 { VEX_W_TABLE (VEX_W_0F3835_P_2) }, 5756 }, 5757 5758 /* PREFIX_VEX_0F3836 */ 5759 { 5760 { Bad_Opcode }, 5761 { Bad_Opcode }, 5762 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, 5763 }, 5764 5765 /* PREFIX_VEX_0F3837 */ 5766 { 5767 { Bad_Opcode }, 5768 { Bad_Opcode }, 5769 { VEX_W_TABLE (VEX_W_0F3837_P_2) }, 5770 }, 5771 5772 /* PREFIX_VEX_0F3838 */ 5773 { 5774 { Bad_Opcode }, 5775 { Bad_Opcode }, 5776 { VEX_W_TABLE (VEX_W_0F3838_P_2) }, 5777 }, 5778 5779 /* PREFIX_VEX_0F3839 */ 5780 { 5781 { Bad_Opcode }, 5782 { Bad_Opcode }, 5783 { VEX_W_TABLE (VEX_W_0F3839_P_2) }, 5784 }, 5785 5786 /* PREFIX_VEX_0F383A */ 5787 { 5788 { Bad_Opcode }, 5789 { Bad_Opcode }, 5790 { VEX_W_TABLE (VEX_W_0F383A_P_2) }, 5791 }, 5792 5793 /* PREFIX_VEX_0F383B */ 5794 { 5795 { Bad_Opcode }, 5796 { Bad_Opcode }, 5797 { VEX_W_TABLE (VEX_W_0F383B_P_2) }, 5798 }, 5799 5800 /* PREFIX_VEX_0F383C */ 5801 { 5802 { Bad_Opcode }, 5803 { Bad_Opcode }, 5804 { VEX_W_TABLE (VEX_W_0F383C_P_2) }, 5805 }, 5806 5807 /* PREFIX_VEX_0F383D */ 5808 { 5809 { Bad_Opcode }, 5810 { Bad_Opcode }, 5811 { VEX_W_TABLE (VEX_W_0F383D_P_2) }, 5812 }, 5813 5814 /* PREFIX_VEX_0F383E */ 5815 { 5816 { Bad_Opcode }, 5817 { Bad_Opcode }, 5818 { VEX_W_TABLE (VEX_W_0F383E_P_2) }, 5819 }, 5820 5821 /* PREFIX_VEX_0F383F */ 5822 { 5823 { Bad_Opcode }, 5824 { Bad_Opcode }, 5825 { VEX_W_TABLE (VEX_W_0F383F_P_2) }, 5826 }, 5827 5828 /* PREFIX_VEX_0F3840 */ 5829 { 5830 { Bad_Opcode }, 5831 { Bad_Opcode }, 5832 { VEX_W_TABLE (VEX_W_0F3840_P_2) }, 5833 }, 5834 5835 /* PREFIX_VEX_0F3841 */ 5836 { 5837 { Bad_Opcode }, 5838 { Bad_Opcode }, 5839 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, 5840 }, 5841 5842 /* PREFIX_VEX_0F3845 */ 5843 { 5844 { Bad_Opcode }, 5845 { Bad_Opcode }, 5846 { "vpsrlv%LW", { XM, Vex, EXx } }, 5847 }, 5848 5849 /* PREFIX_VEX_0F3846 */ 5850 { 5851 { Bad_Opcode }, 5852 { Bad_Opcode }, 5853 { VEX_W_TABLE (VEX_W_0F3846_P_2) }, 5854 }, 5855 5856 /* PREFIX_VEX_0F3847 */ 5857 { 5858 { Bad_Opcode }, 5859 { Bad_Opcode }, 5860 { "vpsllv%LW", { XM, Vex, EXx } }, 5861 }, 5862 5863 /* PREFIX_VEX_0F3858 */ 5864 { 5865 { Bad_Opcode }, 5866 { Bad_Opcode }, 5867 { VEX_W_TABLE (VEX_W_0F3858_P_2) }, 5868 }, 5869 5870 /* PREFIX_VEX_0F3859 */ 5871 { 5872 { Bad_Opcode }, 5873 { Bad_Opcode }, 5874 { VEX_W_TABLE (VEX_W_0F3859_P_2) }, 5875 }, 5876 5877 /* PREFIX_VEX_0F385A */ 5878 { 5879 { Bad_Opcode }, 5880 { Bad_Opcode }, 5881 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, 5882 }, 5883 5884 /* PREFIX_VEX_0F3878 */ 5885 { 5886 { Bad_Opcode }, 5887 { Bad_Opcode }, 5888 { VEX_W_TABLE (VEX_W_0F3878_P_2) }, 5889 }, 5890 5891 /* PREFIX_VEX_0F3879 */ 5892 { 5893 { Bad_Opcode }, 5894 { Bad_Opcode }, 5895 { VEX_W_TABLE (VEX_W_0F3879_P_2) }, 5896 }, 5897 5898 /* PREFIX_VEX_0F388C */ 5899 { 5900 { Bad_Opcode }, 5901 { Bad_Opcode }, 5902 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, 5903 }, 5904 5905 /* PREFIX_VEX_0F388E */ 5906 { 5907 { Bad_Opcode }, 5908 { Bad_Opcode }, 5909 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, 5910 }, 5911 5912 /* PREFIX_VEX_0F3890 */ 5913 { 5914 { Bad_Opcode }, 5915 { Bad_Opcode }, 5916 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, 5917 }, 5918 5919 /* PREFIX_VEX_0F3891 */ 5920 { 5921 { Bad_Opcode }, 5922 { Bad_Opcode }, 5923 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, 5924 }, 5925 5926 /* PREFIX_VEX_0F3892 */ 5927 { 5928 { Bad_Opcode }, 5929 { Bad_Opcode }, 5930 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, 5931 }, 5932 5933 /* PREFIX_VEX_0F3893 */ 5934 { 5935 { Bad_Opcode }, 5936 { Bad_Opcode }, 5937 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, 5938 }, 5939 5940 /* PREFIX_VEX_0F3896 */ 5941 { 5942 { Bad_Opcode }, 5943 { Bad_Opcode }, 5944 { "vfmaddsub132p%XW", { XM, Vex, EXx } }, 5945 }, 5946 5947 /* PREFIX_VEX_0F3897 */ 5948 { 5949 { Bad_Opcode }, 5950 { Bad_Opcode }, 5951 { "vfmsubadd132p%XW", { XM, Vex, EXx } }, 5952 }, 5953 5954 /* PREFIX_VEX_0F3898 */ 5955 { 5956 { Bad_Opcode }, 5957 { Bad_Opcode }, 5958 { "vfmadd132p%XW", { XM, Vex, EXx } }, 5959 }, 5960 5961 /* PREFIX_VEX_0F3899 */ 5962 { 5963 { Bad_Opcode }, 5964 { Bad_Opcode }, 5965 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 5966 }, 5967 5968 /* PREFIX_VEX_0F389A */ 5969 </