/toolchain/binutils/binutils-2.25/ld/testsuite/ld-x86-64/ |
bnd-ifunc-1.d | 1 #as: --64 -madd-bnd-prefix
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
mips4010.s | 8 madd $4,$5
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mips4010.d | 12 0+000c <stuff\+0xc> madd a0,a1
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set-arch.s | 11 madd $4,$5 49 madd.d $f0,$f2,$f4,$f6 50 madd.s $f0,$f2,$f4,$f6 128 madd.ps $f20, $f22, $f24, $f26 157 madd $5, $6
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mips4-fp.s | 11 madd.d $f0,$f2,$f4,$f6 13 madd.s $f10,$f8,$f2,$f0
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r5900.d | 78 [0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31 79 [0-9a-f]+ <[^>]*> 73e0f800 madd \$31,\$31,\$0 80 [0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31 81 [0-9a-f]+ <[^>]*> 73e00000 madd \$31,\$0
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mips4-fp.d | 19 [0-9a-f]+ <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6 20 [0-9a-f]+ <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
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mips32.d | 12 0+0008 <[^>]*> 70a60000 madd a1,a2
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micromips@mips4-fp.d | 24 [0-9a-f]+ <[^>]*> 54c4 0089 madd\.d \$f0,\$f2,\$f4,\$f6 25 [0-9a-f]+ <[^>]*> 5402 5201 madd\.s \$f10,\$f8,\$f2,\$f0
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mips32.s | 14 madd $5, $6
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
mpx-add-bnd-prefix.s | 1 # Check -madd-bnd-prefix option 17 # -madd-bnd-prefix is specified
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x86-64-mpx-add-bnd-prefix.s | 1 # Check -madd-bnd-prefix option 17 # -madd-bnd-prefix is specified
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mpx-add-bnd-prefix.d | 1 #as: -madd-bnd-prefix 3 #name: Check -madd-bnd-prefix
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x86-64-mpx-add-bnd-prefix.d | 1 #as: -madd-bnd-prefix 3 #name: Check -madd-bnd-prefix (x86-64)
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/system/core/libpixelflinger/arch-arm64/ |
col32cb16blend.S | 71 madd w6, w6, w5, w10 // dest red * alpha + src red 72 madd w7, w7, w5, w12 // dest green * alpha + src green 73 madd w8, w8, w5, w4 // dest blue * alpha + src blue
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/external/llvm/test/MC/Mips/ |
micromips-multiply-instructions.s | 12 # CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb] 19 # CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c] 23 madd $4, $5
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/toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
erratum835769.s | 36 madd x5, x2, x3, x6 60 madd x5, x4, x3, x6 72 madd x5, x4, x3, x6
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erratum835769.d | 24 [ \t0-9a-f]+:[ \t]+9b031885[ \t]+madd[ \t]+x5, x4, x3, x6 38 [ \t0-9a-f]+:[ \t]+9b031885[ \t]+madd[ \t]+x5, x4, x3, x6 46 [ \t0-9a-f]+:[ \t]+9b031845[ \t]+madd[ \t]+x5, x2, x3, x6
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erratum843419.s | 47 madd x5, x2, x3, x6
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/external/llvm/test/MC/Mips/mips32r6/ |
invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips32.s | 10 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 11 madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/valgrind/none/tests/mips64/ |
fpu_arithmetic.stdout.exp | [all...] |
/external/llvm/test/MC/Mips/mips5/ |
invalid-mips64.s | 16 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 17 madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/clang/test/SemaCXX/ |
vector-casts.cpp | 61 void madd(const testvec& rhs) { function in struct:testvec
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/external/llvm/test/MC/Mips/mips4/ |
invalid-mips64.s | 15 madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 16 madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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