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      1 	.text
      2 
      3 	.set noreorder
      4 	.set noat
      5 
      6 	.set arch=4010
      7 
      8 	flushi
      9 	flushd
     10 	flushid
     11 	madd $4,$5
     12 	maddu $5,$6
     13 	ffc $6,$7
     14 	ffs $7,$8
     15 	msub $8,$9
     16 	msubu $9,$10
     17 	selsl $10,$11,$12
     18 	selsr $11,$12,$13
     19 	waiti
     20 	wb 16($14)
     21 	addciu $14,$15,16
     22 
     23 	.set arch=4100
     24 
     25 	hibernate
     26 	standby
     27 	suspend
     28 
     29 	.set arch=4650
     30 
     31 	mad $4,$5
     32 	madu $5,$6
     33 	mul $6,$7,$8
     34 
     35 	# test mips4 instructions.
     36 
     37 	.set arch=mips4
     38 
     39 text_label:
     40 	bc1f	text_label
     41 	bc1f	$fcc1,text_label
     42 	bc1fl	$fcc1,text_label
     43 	bc1t	$fcc1,text_label
     44 	bc1tl	$fcc2,text_label
     45 	c.f.d	$f4,$f6
     46 	c.f.d	$fcc1,$f4,$f6
     47 	ldxc1	$f2,$4($5)
     48 	lwxc1	$f2,$4($5)
     49 	madd.d	$f0,$f2,$f4,$f6
     50 	madd.s	$f0,$f2,$f4,$f6
     51 	movf	$4,$5,$fcc4
     52 	movf.d	$f4,$f6,$fcc0
     53 	movf.s	$f4,$f6,$fcc0
     54 	movn	$4,$6,$6
     55 	movn.d	$f4,$f6,$6
     56 	movn.s	$f4,$f6,$6
     57 	movt	$4,$5,$fcc4
     58 	movt.d	$f4,$f6,$fcc0
     59 	movt.s	$f4,$f6,$fcc0
     60 	movz	$4,$6,$6
     61 	movz.d	$f4,$f6,$6
     62 	movz.s	$f4,$f6,$6
     63 	msub.d	$f0,$f2,$f4,$f6
     64 	msub.s	$f0,$f2,$f4,$f6
     65 	nmadd.d	$f0,$f2,$f4,$f6
     66 	nmadd.s	$f0,$f2,$f4,$f6
     67 	nmsub.d	$f0,$f2,$f4,$f6
     68 	nmsub.s	$f0,$f2,$f4,$f6
     69 
     70 	# We don't test pref because currently the disassembler will
     71 	# disassemble it as lwc3.  lwc3 is correct for mips1 to mips3,
     72 	# while pref is correct for mips4.  Unfortunately, the
     73 	# disassembler does not know which architecture it is
     74 	# disassembling for.
     75 	# pref	4,0($4)
     76 
     77 	prefx	4,$4($5)
     78 	recip.d	$f4,$f6
     79 	recip.s	$f4,$f6
     80 	rsqrt.d	$f4,$f6
     81 	rsqrt.s	$f4,$f6
     82 	sdxc1	$f4,$4($5)
     83 	swxc1	$f4,$4($5)
     84 
     85 	# test mips5 instructions.
     86 
     87 	.set arch=mips5
     88 
     89 	abs.ps		$f0, $f2
     90 	add.ps		$f2, $f4, $f6
     91 	alnv.ps		$f6, $f8, $f10, $3
     92 	c.eq.ps		$f8, $f10
     93 	c.eq.ps		$fcc2, $f10, $f12
     94 	c.f.ps	    	$f8, $f10
     95 	c.f.ps	    	$fcc2, $f10, $f12
     96 	c.le.ps		$f8, $f10
     97 	c.le.ps		$fcc2, $f10, $f12
     98 	c.lt.ps		$f8, $f10
     99 	c.lt.ps		$fcc2, $f10, $f12
    100 	c.nge.ps	$f8, $f10
    101 	c.nge.ps	$fcc2, $f10, $f12
    102 	c.ngl.ps	$f8, $f10
    103 	c.ngl.ps	$fcc2, $f10, $f12
    104 	c.ngle.ps	$f8, $f10
    105 	c.ngle.ps	$fcc2, $f10, $f12
    106 	c.ngt.ps	$f8, $f10
    107 	c.ngt.ps	$fcc2, $f10, $f12
    108 	c.ole.ps	$f8, $f10
    109 	c.ole.ps	$fcc2, $f10, $f12
    110 	c.olt.ps	$f8, $f10
    111 	c.olt.ps	$fcc2, $f10, $f12
    112 	c.seq.ps	$f8, $f10
    113 	c.seq.ps	$fcc2, $f10, $f12
    114 	c.sf.ps		$f8, $f10
    115 	c.sf.ps		$fcc2, $f10, $f12
    116 	c.ueq.ps	$f8, $f10
    117 	c.ueq.ps	$fcc2, $f10, $f12
    118 	c.ule.ps	$f8, $f10
    119 	c.ule.ps	$fcc2, $f10, $f12
    120 	c.ult.ps	$f8, $f10
    121 	c.ult.ps	$fcc2, $f10, $f12
    122 	c.un.ps		$f8, $f10
    123 	c.un.ps		$fcc2, $f10, $f12
    124 	cvt.ps.s	$f12, $f14, $f16
    125 	cvt.s.pl	$f16, $f18
    126 	cvt.s.pu	$f18, $f20
    127 	luxc1		$f20, $4($5)
    128 	madd.ps		$f20, $f22, $f24, $f26
    129 	mov.ps		$f24, $f26
    130 	movf.ps		$f26, $f28, $fcc2
    131 	movn.ps		$f26, $f28, $3
    132 	movt.ps		$f28, $f30, $fcc4
    133 	movz.ps		$f28, $f30, $5
    134 	msub.ps		$f30, $f0, $f2, $f4
    135 	mul.ps		$f2, $f4, $f6
    136 	neg.ps		$f6, $f8
    137 	nmadd.ps	$f6, $f8, $f10, $f12
    138 	nmsub.ps	$f6, $f8, $f10, $f12
    139 	pll.ps		$f10, $f12, $f14
    140 	plu.ps		$f14, $f16, $f18
    141 	pul.ps		$f16, $f18, $f20
    142 	puu.ps		$f20, $f22, $f24
    143 	sub.ps		$f22, $f24, $f26
    144 	suxc1		$f26, $6($7)
    145 
    146 	c.eq.ps		$fcc3, $f10, $f12	# warns
    147 	movf.ps		$f26, $f28, $fcc3	# warns
    148 
    149 	# test assembly of mips32 instructions
    150 
    151 	.set arch=mips32
    152 
    153 	# unprivileged CPU instructions
    154 
    155 	clo     $1, $2
    156 	clz     $3, $4
    157 	madd    $5, $6
    158 	maddu   $7, $8
    159 	msub    $9, $10
    160 	msubu   $11, $12
    161 	mul     $13, $14, $15
    162 	pref    4, ($16)
    163 	pref    4, 32767($17)
    164 	pref    4, -32768($18)
    165 	ssnop
    166 
    167 	# unprivileged coprocessor instructions.
    168 	# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
    169 
    170 	bc2f    text_label
    171 	nop
    172 	bc2fl   text_label
    173 	nop
    174 	bc2t    text_label
    175 	nop
    176 	bc2tl   text_label
    177 	nop
    178 	# XXX other BCzCond encodings not currently expressable
    179 	cfc2    $1, $2
    180 	cop2    0x1234567               # disassembles as c2 ...
    181 	ctc2    $2, $3
    182 	mfc2    $3, $4
    183 	mfc2    $4, $5, 0               # disassembles without sel
    184 	mfc2    $5, $6, 7
    185 	mtc2    $6, $7
    186 	mtc2    $7, $8, 0               # disassembles without sel
    187 	mtc2    $8, $9, 7
    188 
    189 	# privileged instructions
    190 
    191 	cache   5, ($1)
    192 	cache   5, 32767($2)
    193 	cache   5, -32768($3)
    194 	eret
    195 	tlbp
    196 	tlbr
    197 	tlbwi
    198 	tlbwr
    199 	wait
    200 	wait    0                       # disassembles without code
    201 	wait    0x56789
    202 
    203 	# For a while break for the mips32 ISA interpreted a single argument
    204 	# as a 20-bit code, placing it in the opcode differently to
    205 	# traditional ISAs.  This turned out to cause problems, so it has
    206 	# been removed.  This test is to assure consistent interpretation.
    207 	break
    208 	break   0                       # disassembles without code
    209 	break	0x345
    210 	break	0x48,0x345		# this still specifies a 20-bit code
    211 
    212 	# Instructions in previous ISAs or CPUs which are now slightly
    213 	# different.
    214 	sdbbp
    215 	sdbbp   0                       # disassembles without code
    216 	sdbbp   0x56789
    217 
    218 	# test assembly of mips32r2 instructions
    219 
    220 	.set arch=mips32r2
    221 
    222 	# unprivileged CPU instructions
    223 
    224 	ehb
    225 
    226 	ext	$4, $5, 6, 8
    227 
    228 	ins	$4, $5, 6, 8
    229 
    230 	jalr.hb	$8
    231 	jalr.hb $20, $9
    232 
    233 	jr.hb	$8
    234 
    235 	# Note, further testing of rdhwr is done in hwr-names-mips32r2.d
    236 	rdhwr	$10, $0
    237 	rdhwr	$11, $1
    238 	rdhwr	$12, $2
    239 	rdhwr	$13, $3
    240 	rdhwr	$14, $4
    241 	rdhwr	$15, $5
    242 
    243 	# This file checks that in fact HW rotate will
    244 	# be used for this arch, and checks assembly
    245 	# of the official MIPS mnemonics.  (Note that disassembly
    246 	# uses the traditional "ror" and "rorv" mnemonics.)
    247 	# Additional rotate tests are done by rol-hw.d.
    248 	rotl	$25, $10, 4
    249 	rotr	$25, $10, 4
    250 	rotl	$25, $10, $4
    251 	rotr	$25, $10, $4
    252 	rotrv	$25, $10, $4
    253 
    254 	seb	$7
    255 	seb	$8, $10
    256 
    257 	seh	$7
    258 	seh	$8, $10
    259 
    260 	synci	0x5555($10)
    261 
    262 	wsbh	$7
    263 	wsbh	$8, $10
    264 
    265 	# cp0 instructions
    266 
    267 	di
    268 	di	$0
    269 	di	$10
    270 
    271 	ei
    272 	ei	$0
    273 	ei	$10
    274 
    275 	rdpgpr	$10, $25
    276 
    277 	wrpgpr	$10, $25
    278 
    279 	# FPU (cp1) instructions
    280 	#
    281 	# Even registers are supported w/ 32-bit FPU, odd
    282 	# registers supported only for 64-bit FPU.
    283 	# Only the 32-bit FPU instructions are tested here.
    284 
    285 	mfhc1	$17, $f0
    286 	mthc1	$17, $f0
    287 
    288 	# cp2 instructions
    289 
    290 	mfhc2	$17, 0x5555
    291 	mthc2	$17, 0x5555
    292 
    293 	.set arch=mips64
    294 
    295 	# test assembly of mips64 instructions
    296 
    297 	# unprivileged CPU instructions
    298 
    299 	dclo    $1, $2
    300 	dclz    $3, $4
    301 
    302 	# unprivileged coprocessor instructions.
    303 	# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
    304 
    305 	dmfc2   $3, $4
    306 	dmfc2   $4, $5, 0               # disassembles without sel
    307 	dmfc2   $5, $6, 7
    308 	dmtc2   $6, $7
    309 	dmtc2   $7, $8, 0               # disassembles without sel
    310 	dmtc2   $8, $9, 7
    311 
    312 	.set arch=vr4111
    313 
    314 	dmadd16	$4,$5
    315 	madd16	$5,$6
    316 
    317 	.set arch=vr4120
    318 
    319 	# Include mflos to check for nop insertion.
    320 	mflo        $4
    321 	dmacc       $4,$5,$6
    322 	dmacchi     $4,$5,$6
    323 	dmacchis    $4,$5,$6
    324 	dmacchiu    $4,$5,$6
    325 	dmacchius   $4,$5,$6
    326 	dmaccs      $4,$5,$6
    327 	dmaccu      $4,$5,$6
    328 	dmaccus     $4,$5,$6
    329 	mflo        $4
    330 	macc        $4,$5,$6
    331 	macchi      $4,$5,$6
    332 	macchis     $4,$5,$6
    333 	macchiu     $4,$5,$6
    334 	macchius    $4,$5,$6
    335 	maccs       $4,$5,$6
    336 	maccu       $4,$5,$6
    337 	maccus      $4,$5,$6
    338 
    339 	.set arch=vr5400
    340 
    341 	/* Integer instructions.  */
    342 
    343 	mulu	$4,$5,$6
    344 	mulhi	$4,$5,$6
    345 	mulhiu	$4,$5,$6
    346 	muls	$4,$5,$6
    347 	mulsu	$4,$5,$6
    348 	mulshi	$4,$5,$6
    349 	mulshiu	$4,$5,$6
    350 	macc	$4,$5,$6
    351 	maccu	$4,$5,$6
    352 	macchi	$4,$5,$6
    353 	macchiu	$4,$5,$6
    354 	msac	$4,$5,$6
    355 	msacu	$4,$5,$6
    356 	msachi	$4,$5,$6
    357 	msachiu	$4,$5,$6
    358 
    359 	ror	$4,$5,25
    360 	rorv	$4,$5,$6
    361 	dror	$4,$5,25
    362 	dror	$4,$5,57	/* Should expand to dror32 $4,$5,25.  */
    363 	dror32	$4,$5,25
    364 	drorv	$4,$5,$6
    365 
    366 	/* Debug instructions.  */
    367 
    368 	dbreak
    369 	dret
    370 	mfdr	$3,$3
    371 	mtdr	$3,$3
    372 
    373 	/* Coprocessor 0 instructions, minus standard ISA 3 ones.
    374 	   That leaves just the performance monitoring registers.  */
    375 
    376 	mfpc	$4,1
    377 	mfps	$4,1
    378 	mtpc	$4,1
    379 	mtps	$4,1
    380 
    381 	/* Multimedia instructions.  */
    382 
    383 	.macro	nsel2 op
    384 	/* Test each form of each vector opcode.  */
    385 	\op	$f0,$f2
    386 	\op	$f4,$f6[2]
    387 	\op	$f6,15
    388 	.if 0	/* Which is right?? */
    389 	/* Test negative numbers in immediate-value slot.  */
    390 	\op	$f4,-3
    391 	.else
    392 	/* Test that it's recognized as an unsigned field.  */
    393 	\op	$f4,31
    394 	.endif
    395 	.endm
    396 
    397 	.macro	nsel3 op
    398 	/* Test each form of each vector opcode.  */
    399 	\op	$f0,$f2,$f4
    400 	\op	$f2,$f4,$f6[2]
    401 	\op	$f6,$f4,15
    402 	.if 0	/* Which is right?? */
    403 	/* Test negative numbers in immediate-value slot.  */
    404 	\op	$f4,$f6,-3
    405 	.else
    406 	/* Test that it's recognized as an unsigned field.  */
    407 	\op	$f4,$f6,31
    408 	.endif
    409 	.endm
    410 
    411 	nsel3	add.ob
    412 	nsel3	and.ob
    413 	nsel2	c.eq.ob
    414 	nsel2	c.le.ob
    415 	nsel2	c.lt.ob
    416 	nsel3	max.ob
    417 	nsel3	min.ob
    418 	nsel3	mul.ob
    419 	nsel2	mula.ob
    420 	nsel2	mull.ob
    421 	nsel2	muls.ob
    422 	nsel2	mulsl.ob
    423 	nsel3	nor.ob
    424 	nsel3	or.ob
    425 	nsel3	pickf.ob
    426 	nsel3	pickt.ob
    427 	nsel3	sub.ob
    428 	nsel3	xor.ob
    429 
    430 	/* ALNI, SHFL: Vector only.  */
    431 	alni.ob		$f0,$f2,$f4,5
    432 	shfl.mixh.ob	$f0,$f2,$f4
    433 	shfl.mixl.ob	$f0,$f2,$f4
    434 	shfl.pach.ob	$f0,$f2,$f4
    435 	shfl.pacl.ob	$f0,$f2,$f4
    436 
    437 	/* SLL,SRL: Scalar or immediate.  */
    438 	sll.ob	$f2,$f4,$f6[3]
    439 	sll.ob	$f4,$f6,14
    440 	srl.ob	$f2,$f4,$f6[3]
    441 	srl.ob	$f4,$f6,14
    442 
    443 	/* RZU: Immediate, must be 0, 8, or 16.  */
    444 	rzu.ob	$f2,13
    445 
    446 	/* No selector.  */
    447 	rach.ob	$f2
    448 	racl.ob	$f2
    449 	racm.ob	$f2
    450 	wach.ob	$f2
    451 	wacl.ob	$f2,$f4
    452 
    453 	ror	$4,$5,$6
    454 	rol	$4,$5,15
    455 	dror	$4,$5,$6
    456 	drol	$4,$5,31
    457 	drol	$4,$5,62
    458 
    459 	.set arch=vr5500
    460 
    461 	/* Prefetch instructions.  */
    462         # We don't test pref because currently the disassembler will
    463         # disassemble it as lwc3.  lwc3 is correct for mips1 to mips3,
    464         # while pref is correct for mips4.  Unfortunately, the
    465         # disassembler does not know which architecture it is
    466         # disassembling for.
    467         # pref  4,0($4)
    468 
    469         prefx   4,$4($5)
    470 
    471 	/* Miscellaneous instructions.  */
    472 
    473 	wait
    474 	wait	0		# disassembles without code
    475 	wait	0x56789
    476 
    477 	ssnop
    478 
    479 	clo	$3,$4
    480 	dclo	$3,$4
    481 	clz	$3,$4
    482 	dclz    $3,$4
    483 
    484 	luxc1	$f0,$4($2)
    485 	suxc1   $f2,$4($2)
    486 
    487 	tlbp
    488 	tlbr
    489 
    490 .set arch=default
    491 
    492 # make objdump print ...
    493 	.space 8
    494