| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 318 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
319 if (DefMI.getParent() != BB || DefMI.isDebugValue())
322 Ret = &DefMI;
323 else if (Ret != &DefMI)
447 MachineInstr *DefMI = &MI;
453 if (!isPlainlyKilled(DefMI, Reg, LIS))
462 DefMI = Begin->getParent();
467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| MachineScheduler.cpp | [all...] |
| RegisterCoalescer.cpp | 664 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
665 if (!DefMI)
667 if (!DefMI->isCommutable())
669 // If DefMI is a two-address instruction then commuting it will change the
671 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
674 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
687 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
690 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
715 << *DefMI);
719 MachineBasicBlock *MBB = DefMI->getParent()
[all...] |
| MachinePipeliner.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| InlineSpiller.cpp | 108 MachineInstr *DefMI;
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
122 bool hasDef() const { return DefByOrigPHI || DefMI; }
331 if (SVI.DefMI)
332 OS << " def: " << *SVI.DefMI;
395 DepSV.DefMI = SV.DefMI;
484 return SVI->second.DefMI;
602 SVI->second.DefMI = MI;
623 return SVI->second.DefMI;
[all...] |
| TwoAddressInstructionPass.cpp | 91 MachineInstr *MI, MachineInstr *DefMI,
308 MachineInstr *MI, MachineInstr *DefMI,
334 return MBB == DefMI->getParent();
429 MachineInstr *DefMI = &MI;
431 if (!DefMI->killsRegister(Reg))
440 DefMI = &*Begin;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| LiveIntervalAnalysis.cpp | 277 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
278 if (DefMI != 0) {
279 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 291 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
292 if (!DefMI->isFullCopy())
294 VReg = DefMI->getOperand(1).getReg();
309 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
312 switch (DefMI->getOpcode()) {
316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
322 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
323 DefMI->getOperand(3).getImm() != 0)
332 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
