| /external/valgrind/none/tests/ppc64/ |
| jm-int.stdout.exp | [all...] |
| jm-int.stdout.exp-LE | [all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativePPC_64.c | 245 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)));
249 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| 476.s | 9 adde 3,4,5
10 adde. 3,4,5
|
| a2.s | 9 adde. 4,5,6
10 adde 4,5,6
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 98 setOperationAction(ISD::ADDE, MVT::i32, Custom);
422 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
471 case ISD::ADDE:
|
| /external/valgrind/VEX/priv/ |
| guest_ppc_defs.h | 122 /* 1 */ PPCG_FLAG_OP_ADDE, // adde[o], addme[o], addze[o]
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.td | 368 defm ADDC_ : ALUarith<0b001, "addc", adde, i32lo16z, i32hi16>;
372 def : Pat<(adde GPR:$Rs1, i32lo16z:$imm),
378 def : Pat<(adde GPR:$Rs1, i32hi16:$imm),
394 defm ADDC_F_ : ALUarith<0b001, "addc.f", adde, i32lo16z, i32hi16>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 363 "adde $rT, $rA, $rB", IntGeneral,
364 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
367 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
370 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
[all...] |
| PPCSchedule.td | 119 // adde IntGeneral
|
| PPCInstrInfo.td | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 227 case ISD::ADDE: return "adde";
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| ppc64-encoding.txt | 268 # CHECK: adde 2, 3, 4
271 # CHECK: adde. 2, 3, 4
|
| ppc64le-encoding.txt | 265 # CHECK: adde 2, 3, 4
268 # CHECK: adde. 2, 3, 4
|
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| ppc64.s | 236 ADDE R1, R2, R3
242 ADDE R1, R2
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| ppc64.s | 236 ADDE R1, R2, R3
242 ADDE R1, R2
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
739 case ISD::ADDE: {
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand);
213 setOperationAction(ISD::ADDE, MVT::Other, Expand);
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding.s | 338 # CHECK-BE: adde 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x14]
339 # CHECK-LE: adde 2, 3, 4 # encoding: [0x14,0x21,0x43,0x7c]
340 adde 2, 3, 4
341 # CHECK-BE: adde. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x15]
342 # CHECK-LE: adde. 2, 3, 4 # encoding: [0x15,0x21,0x43,0x7c]
343 adde. 2, 3, 4
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMISelLowering.h | 72 ADDE, // Add using carry
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRInstrInfo.td | 354 [(set i8:$rd, (adde i8:$src, i8:$rr)),
368 [(set i16:$rd, (adde i16:$src, i16:$rr)),
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 91 setOperationAction(ISD::ADDE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 531 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
532 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
535 [(set i64:$rT, (adde i64:$rA, -1))]>;
538 [(set i64:$rT, (adde i64:$rA, 0))]>;
[all...] |
