1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PowerPC 64-bit instructions. These patterns are used 11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // 64-bit operands. 17 // 18 def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23 } 24 def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 } 30 def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38 } 39 def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41 } 42 def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45 } 46 def tlsgd : Operand<i64> {} 47 def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51 } 52 53 //===----------------------------------------------------------------------===// 54 // 64-bit transformation functions. 55 // 56 57 def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60 }]>; 61 62 def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66 }]>; 67 68 def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); 71 }]>; 72 73 def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); 76 }]>; 77 78 79 //===----------------------------------------------------------------------===// 80 // Calls. 81 // 82 83 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isReturn = 1, Uses = [LR8, RM] in 86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 87 [(retflag)]>, Requires<[In64BitMode]>; 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 94 []>, 95 Requires<[In64BitMode]>; 96 97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 98 "bcctr 12, $bi, 0", IIC_BrB, []>, 99 Requires<[In64BitMode]>; 100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 101 "bcctr 4, $bi, 0", IIC_BrB, []>, 102 Requires<[In64BitMode]>; 103 } 104 } 105 106 let Defs = [LR8] in 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 108 PPC970_Unit_BRU; 109 110 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 111 let Defs = [CTR8], Uses = [CTR8] in { 112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 113 "bdz $dst">; 114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 115 "bdnz $dst">; 116 } 117 118 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 120 "bdzlr", IIC_BrB, []>; 121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 122 "bdnzlr", IIC_BrB, []>; 123 } 124 } 125 126 127 128 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 129 // Convenient aliases for call instructions 130 let Uses = [RM] in { 131 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 132 "bl $func", IIC_BrB, []>; // See Pat patterns below. 133 134 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 135 "bl $func", IIC_BrB, []>; 136 137 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 138 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 139 } 140 let Uses = [RM], isCodeGenOnly = 1 in { 141 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 142 (outs), (ins calltarget:$func), 143 "bl $func\n\tnop", IIC_BrB, []>; 144 145 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 146 (outs), (ins tlscall:$func), 147 "bl $func\n\tnop", IIC_BrB, []>; 148 149 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 150 (outs), (ins abscalltarget:$func), 151 "bla $func\n\tnop", IIC_BrB, 152 [(PPCcall_nop (i64 imm:$func))]>; 153 } 154 let Uses = [CTR8, RM] in { 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173 } 174 175 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc ixaddr:$src)]>, 182 Requires<[In64BitMode]>; 183 } 184 185 } // Interpretation64Bit 186 187 // FIXME: Duplicating this for the asm parser should be unnecessary, but the 188 // previous definition must be marked as CodeGen only to prevent decoding 189 // conflicts. 190 let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195 // Calls 196 def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201 def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206 // Atomic operations 207 let usesCustomInserter = 1 in { 208 let Defs = [CR0] in { 209 def ATOMIC_LOAD_ADD_I64 : Pseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 211 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_SUB_I64 : Pseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 214 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_OR_I64 : Pseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 217 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_XOR_I64 : Pseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 220 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_AND_I64 : Pseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 223 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_NAND_I64 : Pseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 226 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 227 228 def ATOMIC_CMP_SWAP_I64 : Pseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 230 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 231 232 def ATOMIC_SWAP_I64 : Pseudo< 233 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 234 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 235 } 236 } 237 238 // Instructions to support atomic operations 239 let mayLoad = 1, hasSideEffects = 0 in { 240 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 242 243 // Instruction to support lock versions of atomics 244 // (EH=1 - see Power ISA 2.07 Book II 4.4.2) 245 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 247 248 let hasExtraDefRegAllocReq = 1 in 249 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 250 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 251 Requires<[IsISA3_0]>; 252 } 253 254 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 255 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 256 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 257 258 let mayStore = 1, hasSideEffects = 0 in 259 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 260 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 261 Requires<[IsISA3_0]>; 262 263 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 264 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 265 def TCRETURNdi8 :Pseudo< (outs), 266 (ins calltarget:$dst, i32imm:$offset), 267 "#TC_RETURNd8 $dst $offset", 268 []>; 269 270 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 271 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 272 "#TC_RETURNa8 $func $offset", 273 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 274 275 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 276 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 277 "#TC_RETURNr8 $dst $offset", 278 []>; 279 280 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 281 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 282 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 283 []>, 284 Requires<[In64BitMode]>; 285 286 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 287 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 288 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 289 "b $dst", IIC_BrB, 290 []>; 291 292 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 293 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 294 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 295 "ba $dst", IIC_BrB, 296 []>; 297 } // Interpretation64Bit 298 299 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 300 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 301 302 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 303 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 304 305 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 306 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 307 308 309 // 64-bit CR instructions 310 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 311 let hasSideEffects = 0 in { 312 // mtocrf's input needs to be prepared by shifting by an amount dependent 313 // on the cr register selected. Thus, post-ra anti-dep breaking must not 314 // later change that register assignment. 315 let hasExtraDefRegAllocReq = 1 in { 316 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 317 "mtocrf $FXM, $ST", IIC_BrMCRX>, 318 PPC970_DGroup_First, PPC970_Unit_CRU; 319 320 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 321 // is dependent on the cr fields being set. 322 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 323 "mtcrf $FXM, $rS", IIC_BrMCRX>, 324 PPC970_MicroCode, PPC970_Unit_CRU; 325 } // hasExtraDefRegAllocReq = 1 326 327 // mfocrf's input needs to be prepared by shifting by an amount dependent 328 // on the cr register selected. Thus, post-ra anti-dep breaking must not 329 // later change that register assignment. 330 let hasExtraSrcRegAllocReq = 1 in { 331 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 332 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 333 PPC970_DGroup_First, PPC970_Unit_CRU; 334 335 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 336 // is dependent on the cr fields being copied. 337 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 338 "mfcr $rT", IIC_SprMFCR>, 339 PPC970_MicroCode, PPC970_Unit_CRU; 340 } // hasExtraSrcRegAllocReq = 1 341 } // hasSideEffects = 0 342 343 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 344 let Defs = [CTR8] in 345 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 346 "#EH_SJLJ_SETJMP64", 347 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 348 Requires<[In64BitMode]>; 349 let isTerminator = 1 in 350 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 351 "#EH_SJLJ_LONGJMP64", 352 [(PPCeh_sjlj_longjmp addr:$buf)]>, 353 Requires<[In64BitMode]>; 354 } 355 356 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 357 "mfspr $RT, $SPR", IIC_SprMFSPR>; 358 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 359 "mtspr $SPR, $RT", IIC_SprMTSPR>; 360 361 362 //===----------------------------------------------------------------------===// 363 // 64-bit SPR manipulation instrs. 364 365 let Uses = [CTR8] in { 366 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 367 "mfctr $rT", IIC_SprMFSPR>, 368 PPC970_DGroup_First, PPC970_Unit_FXU; 369 } 370 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 371 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 372 "mtctr $rS", IIC_SprMTSPR>, 373 PPC970_DGroup_First, PPC970_Unit_FXU; 374 } 375 let hasSideEffects = 1, Defs = [CTR8] in { 376 let Pattern = [(int_ppc_mtctr i64:$rS)] in 377 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 378 "mtctr $rS", IIC_SprMTSPR>, 379 PPC970_DGroup_First, PPC970_Unit_FXU; 380 } 381 382 let Pattern = [(set i64:$rT, readcyclecounter)] in 383 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 384 "mfspr $rT, 268", IIC_SprMFTB>, 385 PPC970_DGroup_First, PPC970_Unit_FXU; 386 // Note that encoding mftb using mfspr is now the preferred form, 387 // and has been since at least ISA v2.03. The mftb instruction has 388 // now been phased out. Using mfspr, however, is known not to work on 389 // the POWER3. 390 391 let Defs = [X1], Uses = [X1] in 392 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 393 [(set i64:$result, 394 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 395 def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 396 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 397 398 let Defs = [LR8] in { 399 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 400 "mtlr $rS", IIC_SprMTSPR>, 401 PPC970_DGroup_First, PPC970_Unit_FXU; 402 } 403 let Uses = [LR8] in { 404 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 405 "mflr $rT", IIC_SprMFSPR>, 406 PPC970_DGroup_First, PPC970_Unit_FXU; 407 } 408 } // Interpretation64Bit 409 410 //===----------------------------------------------------------------------===// 411 // Fixed point instructions. 412 // 413 414 let PPC970_Unit = 1 in { // FXU Operations. 415 let Interpretation64Bit = 1 in { 416 let hasSideEffects = 0 in { 417 let isCodeGenOnly = 1 in { 418 419 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 420 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 421 "li $rD, $imm", IIC_IntSimple, 422 [(set i64:$rD, imm64SExt16:$imm)]>; 423 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 424 "lis $rD, $imm", IIC_IntSimple, 425 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 426 } 427 428 // Logical ops. 429 let isCommutable = 1 in { 430 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 431 "nand", "$rA, $rS, $rB", IIC_IntSimple, 432 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 433 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 434 "and", "$rA, $rS, $rB", IIC_IntSimple, 435 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 436 } // isCommutable 437 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 438 "andc", "$rA, $rS, $rB", IIC_IntSimple, 439 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 440 let isCommutable = 1 in { 441 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 442 "or", "$rA, $rS, $rB", IIC_IntSimple, 443 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 444 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 445 "nor", "$rA, $rS, $rB", IIC_IntSimple, 446 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 447 } // isCommutable 448 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 449 "orc", "$rA, $rS, $rB", IIC_IntSimple, 450 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 451 let isCommutable = 1 in { 452 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 453 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 454 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 455 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 456 "xor", "$rA, $rS, $rB", IIC_IntSimple, 457 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 458 } // let isCommutable = 1 459 460 // Logical ops with immediate. 461 let Defs = [CR0] in { 462 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 463 "andi. $dst, $src1, $src2", IIC_IntGeneral, 464 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 465 isDOT; 466 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 467 "andis. $dst, $src1, $src2", IIC_IntGeneral, 468 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 469 isDOT; 470 } 471 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 472 "ori $dst, $src1, $src2", IIC_IntSimple, 473 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 474 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 475 "oris $dst, $src1, $src2", IIC_IntSimple, 476 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 477 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 478 "xori $dst, $src1, $src2", IIC_IntSimple, 479 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 480 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 481 "xoris $dst, $src1, $src2", IIC_IntSimple, 482 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 483 484 let isCommutable = 1 in 485 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 486 "add", "$rT, $rA, $rB", IIC_IntSimple, 487 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 488 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 489 // initial-exec thread-local storage model. We need to forbid r0 here - 490 // while it works for add just fine, the linker can relax this to local-exec 491 // addi, which won't work for r0. 492 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 493 "add $rT, $rA, $rB", IIC_IntSimple, 494 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 495 496 let isCommutable = 1 in 497 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 498 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 499 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 500 PPC970_DGroup_Cracked; 501 502 let Defs = [CARRY] in 503 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 504 "addic $rD, $rA, $imm", IIC_IntGeneral, 505 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 506 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 507 "addi $rD, $rA, $imm", IIC_IntSimple, 508 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 509 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 510 "addis $rD, $rA, $imm", IIC_IntSimple, 511 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 512 513 let Defs = [CARRY] in { 514 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 515 "subfic $rD, $rA, $imm", IIC_IntGeneral, 516 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 517 } 518 defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 519 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 520 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 521 PPC970_DGroup_Cracked; 522 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 523 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 524 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 525 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 526 "neg", "$rT, $rA", IIC_IntSimple, 527 [(set i64:$rT, (ineg i64:$rA))]>; 528 let Uses = [CARRY] in { 529 let isCommutable = 1 in 530 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 531 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 532 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 533 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 534 "addme", "$rT, $rA", IIC_IntGeneral, 535 [(set i64:$rT, (adde i64:$rA, -1))]>; 536 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 537 "addze", "$rT, $rA", IIC_IntGeneral, 538 [(set i64:$rT, (adde i64:$rA, 0))]>; 539 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 540 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 541 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 542 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 543 "subfme", "$rT, $rA", IIC_IntGeneral, 544 [(set i64:$rT, (sube -1, i64:$rA))]>; 545 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 546 "subfze", "$rT, $rA", IIC_IntGeneral, 547 [(set i64:$rT, (sube 0, i64:$rA))]>; 548 } 549 } // isCodeGenOnly 550 551 // FIXME: Duplicating this for the asm parser should be unnecessary, but the 552 // previous definition must be marked as CodeGen only to prevent decoding 553 // conflicts. 554 let isAsmParserOnly = 1 in 555 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 556 "add $rT, $rA, $rB", IIC_IntSimple, []>; 557 558 let isCommutable = 1 in { 559 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 560 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 561 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 562 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 563 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 564 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 565 } // isCommutable 566 } 567 } // Interpretation64Bit 568 569 let isCompare = 1, hasSideEffects = 0 in { 570 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 571 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 572 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 573 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 574 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 575 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 576 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 577 "cmpldi $dst, $src1, $src2", 578 IIC_IntCompare>, isPPC64; 579 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 580 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 581 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 582 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 583 Requires<[IsISA3_0]>; 584 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 585 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 586 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 587 } 588 589 let hasSideEffects = 0 in { 590 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 591 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 592 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 593 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 594 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 595 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 596 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 597 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 598 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 599 600 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 601 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 602 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 603 defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 604 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 605 Requires<[IsISA3_0]>; 606 607 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 608 "extsb", "$rA, $rS", IIC_IntSimple, 609 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 610 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 611 "extsh", "$rA, $rS", IIC_IntSimple, 612 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 613 614 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 615 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 616 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 617 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 618 } // Interpretation64Bit 619 620 // For fast-isel: 621 let isCodeGenOnly = 1 in { 622 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 623 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 624 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 625 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 626 } // isCodeGenOnly for fast-isel 627 628 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 629 "extsw", "$rA, $rS", IIC_IntSimple, 630 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 631 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 632 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 633 "extsw", "$rA, $rS", IIC_IntSimple, 634 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 635 636 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 637 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 638 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 639 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 640 "cntlzd", "$rA, $rS", IIC_IntGeneral, 641 [(set i64:$rA, (ctlz i64:$rS))]>; 642 defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 643 "cnttzd", "$rA, $rS", IIC_IntGeneral, 644 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 645 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 646 "popcntd $rA, $rS", IIC_IntGeneral, 647 [(set i64:$rA, (ctpop i64:$rS))]>; 648 def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 649 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 650 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 651 isPPC64, Requires<[HasBPERMD]>; 652 653 let isCodeGenOnly = 1, isCommutable = 1 in 654 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 655 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 656 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 657 658 // popcntw also does a population count on the high 32 bits (storing the 659 // results in the high 32-bits of the output). We'll ignore that here (which is 660 // safe because we never separately use the high part of the 64-bit registers). 661 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 662 "popcntw $rA, $rS", IIC_IntGeneral, 663 [(set i32:$rA, (ctpop i32:$rS))]>; 664 665 defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 666 "divd", "$rT, $rA, $rB", IIC_IntDivD, 667 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 668 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 669 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 670 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 671 def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 672 "divde $rT, $rA, $rB", IIC_IntDivD, 673 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 674 isPPC64, Requires<[HasExtDiv]>; 675 let Defs = [CR0] in 676 def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 677 "divde. $rT, $rA, $rB", IIC_IntDivD, 678 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 679 isPPC64, Requires<[HasExtDiv]>; 680 def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 681 "divdeu $rT, $rA, $rB", IIC_IntDivD, 682 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 683 isPPC64, Requires<[HasExtDiv]>; 684 let Defs = [CR0] in 685 def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 686 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 687 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 688 isPPC64, Requires<[HasExtDiv]>; 689 let isCommutable = 1 in 690 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 691 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 692 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 693 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 694 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 695 "mulli $rD, $rA, $imm", IIC_IntMulLI, 696 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 697 } 698 699 let hasSideEffects = 0 in { 700 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 701 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 702 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 703 []>, isPPC64, RegConstraint<"$rSi = $rA">, 704 NoEncode<"$rSi">; 705 706 // Rotate instructions. 707 defm RLDCL : MDSForm_1r<30, 8, 708 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 709 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 710 []>, isPPC64; 711 defm RLDCR : MDSForm_1r<30, 9, 712 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 713 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 714 []>, isPPC64; 715 defm RLDICL : MDForm_1r<30, 0, 716 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 717 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 718 []>, isPPC64; 719 // For fast-isel: 720 let isCodeGenOnly = 1 in 721 def RLDICL_32_64 : MDForm_1<30, 0, 722 (outs g8rc:$rA), 723 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 724 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 725 []>, isPPC64; 726 // End fast-isel. 727 defm RLDICR : MDForm_1r<30, 1, 728 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 729 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 730 []>, isPPC64; 731 defm RLDIC : MDForm_1r<30, 2, 732 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 733 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 734 []>, isPPC64; 735 736 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 737 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 738 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 739 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 740 []>; 741 742 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 743 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 744 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 745 []>; 746 747 // RLWIMI can be commuted if the rotate amount is zero. 748 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 749 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 750 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 751 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 752 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 753 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 754 755 let isSelect = 1 in 756 def ISEL8 : AForm_4<31, 15, 757 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 758 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 759 []>; 760 } // Interpretation64Bit 761 } // hasSideEffects = 0 762 } // End FXU Operations. 763 764 765 //===----------------------------------------------------------------------===// 766 // Load/Store instructions. 767 // 768 769 770 // Sign extending loads. 771 let PPC970_Unit = 2 in { 772 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 773 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 774 "lha $rD, $src", IIC_LdStLHA, 775 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 776 PPC970_DGroup_Cracked; 777 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 778 "lwa $rD, $src", IIC_LdStLWA, 779 [(set i64:$rD, 780 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 781 PPC970_DGroup_Cracked; 782 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 783 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 784 "lhax $rD, $src", IIC_LdStLHA, 785 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 786 PPC970_DGroup_Cracked; 787 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 788 "lwax $rD, $src", IIC_LdStLHA, 789 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 790 PPC970_DGroup_Cracked; 791 // For fast-isel: 792 let isCodeGenOnly = 1, mayLoad = 1 in { 793 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 794 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 795 PPC970_DGroup_Cracked; 796 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 797 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 798 PPC970_DGroup_Cracked; 799 } // end fast-isel isCodeGenOnly 800 801 // Update forms. 802 let mayLoad = 1, hasSideEffects = 0 in { 803 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 804 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 805 (ins memri:$addr), 806 "lhau $rD, $addr", IIC_LdStLHAU, 807 []>, RegConstraint<"$addr.reg = $ea_result">, 808 NoEncode<"$ea_result">; 809 // NO LWAU! 810 811 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 812 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 813 (ins memrr:$addr), 814 "lhaux $rD, $addr", IIC_LdStLHAUX, 815 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 816 NoEncode<"$ea_result">; 817 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 818 (ins memrr:$addr), 819 "lwaux $rD, $addr", IIC_LdStLHAUX, 820 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 821 NoEncode<"$ea_result">, isPPC64; 822 } 823 } 824 825 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 826 // Zero extending loads. 827 let PPC970_Unit = 2 in { 828 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 829 "lbz $rD, $src", IIC_LdStLoad, 830 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 831 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 832 "lhz $rD, $src", IIC_LdStLoad, 833 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 834 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 835 "lwz $rD, $src", IIC_LdStLoad, 836 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 837 838 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 839 "lbzx $rD, $src", IIC_LdStLoad, 840 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 841 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 842 "lhzx $rD, $src", IIC_LdStLoad, 843 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 844 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 845 "lwzx $rD, $src", IIC_LdStLoad, 846 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 847 848 849 // Update forms. 850 let mayLoad = 1, hasSideEffects = 0 in { 851 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 852 "lbzu $rD, $addr", IIC_LdStLoadUpd, 853 []>, RegConstraint<"$addr.reg = $ea_result">, 854 NoEncode<"$ea_result">; 855 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 856 "lhzu $rD, $addr", IIC_LdStLoadUpd, 857 []>, RegConstraint<"$addr.reg = $ea_result">, 858 NoEncode<"$ea_result">; 859 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 860 "lwzu $rD, $addr", IIC_LdStLoadUpd, 861 []>, RegConstraint<"$addr.reg = $ea_result">, 862 NoEncode<"$ea_result">; 863 864 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 865 (ins memrr:$addr), 866 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 867 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 868 NoEncode<"$ea_result">; 869 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 870 (ins memrr:$addr), 871 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 872 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 873 NoEncode<"$ea_result">; 874 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 875 (ins memrr:$addr), 876 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 877 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 878 NoEncode<"$ea_result">; 879 } 880 } 881 } // Interpretation64Bit 882 883 884 // Full 8-byte loads. 885 let PPC970_Unit = 2 in { 886 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 887 "ld $rD, $src", IIC_LdStLD, 888 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 889 // The following four definitions are selected for small code model only. 890 // Otherwise, we need to create two instructions to form a 32-bit offset, 891 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 892 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 893 "#LDtoc", 894 [(set i64:$rD, 895 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 896 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 897 "#LDtocJTI", 898 [(set i64:$rD, 899 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 900 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 901 "#LDtocCPT", 902 [(set i64:$rD, 903 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 904 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 905 "#LDtocCPT", 906 [(set i64:$rD, 907 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 908 909 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 910 "ldx $rD, $src", IIC_LdStLD, 911 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 912 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 913 "ldbrx $rD, $src", IIC_LdStLoad, 914 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 915 916 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 917 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 918 "lhbrx $rD, $src", IIC_LdStLoad, []>; 919 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 920 "lwbrx $rD, $src", IIC_LdStLoad, []>; 921 } 922 923 let mayLoad = 1, hasSideEffects = 0 in { 924 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 925 "ldu $rD, $addr", IIC_LdStLDU, 926 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 927 NoEncode<"$ea_result">; 928 929 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 930 (ins memrr:$addr), 931 "ldux $rD, $addr", IIC_LdStLDUX, 932 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 933 NoEncode<"$ea_result">, isPPC64; 934 935 def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 936 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 937 Requires<[IsISA3_0]>; 938 } 939 } 940 941 // Support for medium and large code model. 942 let hasSideEffects = 0 in { 943 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 944 "#ADDIStocHA", []>, isPPC64; 945 let mayLoad = 1 in 946 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 947 "#LDtocL", []>, isPPC64; 948 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 949 "#ADDItocL", []>, isPPC64; 950 } 951 952 // Support for thread-local storage. 953 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 954 "#ADDISgotTprelHA", 955 [(set i64:$rD, 956 (PPCaddisGotTprelHA i64:$reg, 957 tglobaltlsaddr:$disp))]>, 958 isPPC64; 959 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 960 "#LDgotTprelL", 961 [(set i64:$rD, 962 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 963 isPPC64; 964 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 965 (ADD8TLS $in, tglobaltlsaddr:$g)>; 966 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 967 "#ADDIStlsgdHA", 968 [(set i64:$rD, 969 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 970 isPPC64; 971 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 972 "#ADDItlsgdL", 973 [(set i64:$rD, 974 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 975 isPPC64; 976 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is 977 // explicitly defined when this op is created, so not mentioned here. 978 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 979 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 980 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 981 "#GETtlsADDR", 982 [(set i64:$rD, 983 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 984 isPPC64; 985 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 986 // are true defines while the rest of the Defs are clobbers. 987 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 988 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 989 in 990 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 991 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 992 "#ADDItlsgdLADDR", 993 [(set i64:$rD, 994 (PPCaddiTlsgdLAddr i64:$reg, 995 tglobaltlsaddr:$disp, 996 tglobaltlsaddr:$sym))]>, 997 isPPC64; 998 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 999 "#ADDIStlsldHA", 1000 [(set i64:$rD, 1001 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1002 isPPC64; 1003 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1004 "#ADDItlsldL", 1005 [(set i64:$rD, 1006 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1007 isPPC64; 1008 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1009 // explicitly defined when this op is created, so not mentioned here. 1010 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1011 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1012 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1013 "#GETtlsldADDR", 1014 [(set i64:$rD, 1015 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1016 isPPC64; 1017 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1018 // are true defines, while the rest of the Defs are clobbers. 1019 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1020 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1021 in 1022 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 1023 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1024 "#ADDItlsldLADDR", 1025 [(set i64:$rD, 1026 (PPCaddiTlsldLAddr i64:$reg, 1027 tglobaltlsaddr:$disp, 1028 tglobaltlsaddr:$sym))]>, 1029 isPPC64; 1030 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1031 "#ADDISdtprelHA", 1032 [(set i64:$rD, 1033 (PPCaddisDtprelHA i64:$reg, 1034 tglobaltlsaddr:$disp))]>, 1035 isPPC64; 1036 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1037 "#ADDIdtprelL", 1038 [(set i64:$rD, 1039 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1040 isPPC64; 1041 1042 let PPC970_Unit = 2 in { 1043 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1044 // Truncating stores. 1045 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1046 "stb $rS, $src", IIC_LdStStore, 1047 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1048 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1049 "sth $rS, $src", IIC_LdStStore, 1050 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1051 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1052 "stw $rS, $src", IIC_LdStStore, 1053 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1054 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1055 "stbx $rS, $dst", IIC_LdStStore, 1056 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1057 PPC970_DGroup_Cracked; 1058 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1059 "sthx $rS, $dst", IIC_LdStStore, 1060 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1061 PPC970_DGroup_Cracked; 1062 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1063 "stwx $rS, $dst", IIC_LdStStore, 1064 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1065 PPC970_DGroup_Cracked; 1066 } // Interpretation64Bit 1067 1068 // Normal 8-byte stores. 1069 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1070 "std $rS, $dst", IIC_LdStSTD, 1071 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1072 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1073 "stdx $rS, $dst", IIC_LdStSTD, 1074 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1075 PPC970_DGroup_Cracked; 1076 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1077 "stdbrx $rS, $dst", IIC_LdStStore, 1078 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1079 PPC970_DGroup_Cracked; 1080 } 1081 1082 // Stores with Update (pre-inc). 1083 let PPC970_Unit = 2, mayStore = 1 in { 1084 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1085 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1086 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1087 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1088 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1089 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1090 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1091 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1092 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1093 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1094 1095 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1096 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1097 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1098 PPC970_DGroup_Cracked; 1099 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1100 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1101 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1102 PPC970_DGroup_Cracked; 1103 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1104 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1105 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1106 PPC970_DGroup_Cracked; 1107 } // Interpretation64Bit 1108 1109 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1110 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1111 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1112 isPPC64; 1113 1114 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1115 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1116 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1117 PPC970_DGroup_Cracked, isPPC64; 1118 } 1119 1120 // Patterns to match the pre-inc stores. We can't put the patterns on 1121 // the instruction definitions directly as ISel wants the address base 1122 // and offset to be separate operands, not a single complex operand. 1123 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1124 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1125 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1126 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1127 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1128 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1129 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1130 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1131 1132 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1133 (STBUX8 $rS, $ptrreg, $ptroff)>; 1134 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1135 (STHUX8 $rS, $ptrreg, $ptroff)>; 1136 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1137 (STWUX8 $rS, $ptrreg, $ptroff)>; 1138 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1139 (STDUX $rS, $ptrreg, $ptroff)>; 1140 1141 1142 //===----------------------------------------------------------------------===// 1143 // Floating point instructions. 1144 // 1145 1146 1147 let PPC970_Unit = 3, hasSideEffects = 0, 1148 Uses = [RM] in { // FPU Operations. 1149 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1150 "fcfid", "$frD, $frB", IIC_FPGeneral, 1151 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1152 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1153 "fctid", "$frD, $frB", IIC_FPGeneral, 1154 []>, isPPC64; 1155 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1156 "fctidz", "$frD, $frB", IIC_FPGeneral, 1157 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1158 1159 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1160 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1161 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1162 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1163 "fcfids", "$frD, $frB", IIC_FPGeneral, 1164 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1165 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1166 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1167 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1168 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1169 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1170 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1171 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1172 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1173 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1174 } 1175 1176 1177 //===----------------------------------------------------------------------===// 1178 // Instruction Patterns 1179 // 1180 1181 // Extensions and truncates to/from 32-bit regs. 1182 def : Pat<(i64 (zext i32:$in)), 1183 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1184 0, 32)>; 1185 def : Pat<(i64 (anyext i32:$in)), 1186 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1187 def : Pat<(i32 (trunc i64:$in)), 1188 (EXTRACT_SUBREG $in, sub_32)>; 1189 1190 // Implement the 'not' operation with the NOR instruction. 1191 // (we could use the default xori pattern, but nor has lower latency on some 1192 // cores (such as the A2)). 1193 def i64not : OutPatFrag<(ops node:$in), 1194 (NOR8 $in, $in)>; 1195 def : Pat<(not i64:$in), 1196 (i64not $in)>; 1197 1198 // Extending loads with i64 targets. 1199 def : Pat<(zextloadi1 iaddr:$src), 1200 (LBZ8 iaddr:$src)>; 1201 def : Pat<(zextloadi1 xaddr:$src), 1202 (LBZX8 xaddr:$src)>; 1203 def : Pat<(extloadi1 iaddr:$src), 1204 (LBZ8 iaddr:$src)>; 1205 def : Pat<(extloadi1 xaddr:$src), 1206 (LBZX8 xaddr:$src)>; 1207 def : Pat<(extloadi8 iaddr:$src), 1208 (LBZ8 iaddr:$src)>; 1209 def : Pat<(extloadi8 xaddr:$src), 1210 (LBZX8 xaddr:$src)>; 1211 def : Pat<(extloadi16 iaddr:$src), 1212 (LHZ8 iaddr:$src)>; 1213 def : Pat<(extloadi16 xaddr:$src), 1214 (LHZX8 xaddr:$src)>; 1215 def : Pat<(extloadi32 iaddr:$src), 1216 (LWZ8 iaddr:$src)>; 1217 def : Pat<(extloadi32 xaddr:$src), 1218 (LWZX8 xaddr:$src)>; 1219 1220 // Standard shifts. These are represented separately from the real shifts above 1221 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1222 // amounts. 1223 def : Pat<(sra i64:$rS, i32:$rB), 1224 (SRAD $rS, $rB)>; 1225 def : Pat<(srl i64:$rS, i32:$rB), 1226 (SRD $rS, $rB)>; 1227 def : Pat<(shl i64:$rS, i32:$rB), 1228 (SLD $rS, $rB)>; 1229 1230 // SHL/SRL 1231 def : Pat<(shl i64:$in, (i32 imm:$imm)), 1232 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1233 def : Pat<(srl i64:$in, (i32 imm:$imm)), 1234 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1235 1236 // ROTL 1237 def : Pat<(rotl i64:$in, i32:$sh), 1238 (RLDCL $in, $sh, 0)>; 1239 def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1240 (RLDICL $in, imm:$imm, 0)>; 1241 1242 // Hi and Lo for Darwin Global Addresses. 1243 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1244 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1245 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1246 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1247 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1248 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1249 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1250 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1251 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1252 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1253 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1254 (ADDI8 $in, tglobaltlsaddr:$g)>; 1255 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1256 (ADDIS8 $in, tglobaladdr:$g)>; 1257 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1258 (ADDIS8 $in, tconstpool:$g)>; 1259 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1260 (ADDIS8 $in, tjumptable:$g)>; 1261 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1262 (ADDIS8 $in, tblockaddress:$g)>; 1263 1264 // Patterns to match r+r indexed loads and stores for 1265 // addresses without at least 4-byte alignment. 1266 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1267 (LWAX xoaddr:$src)>; 1268 def : Pat<(i64 (unaligned4load xoaddr:$src)), 1269 (LDX xoaddr:$src)>; 1270 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1271 (STDX $rS, xoaddr:$dst)>; 1272 1273 // 64-bits atomic loads and stores 1274 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1275 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1276 1277 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1278 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1279 1280 let Predicates = [IsISA3_0] in { 1281 1282 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1283 InstrItinClass itin, list<dag> pattern> 1284 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1285 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1286 1287 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1288 def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1289 def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1290 def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1291 } 1292 1293 // SLB Invalidate Entry Global 1294 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1295 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1296 // SLB Synchronize 1297 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1298 1299 } // IsISA3_0 1300
