| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 16 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
17 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrFPU.td | 238 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| relax-at.d | 72 000000b0 <foo\+0xb0> bc1t 000000c4 <foo\+0xc4>
265 00020300 <bar\+0xb0> bc1t 00020314 <bar\+0xc4>
|
| relax.d | 71 000000b0 <foo\+0xb0> bc1t 000000c4 <foo\+0xc4>
264 00020300 <bar\+0xb0> bc1t 00020314 <bar\+0xc4>
|
| relax-swap1-mips1.d | 165 0+0204 <[^>]*> bc1t 00000000 <foo>
|
| relax-swap1-mips2.d | 146 0+01b8 <[^>]*> bc1t 00000000 <foo>
|
| set-arch.s | 43 bc1t $fcc1,text_label
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 169 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
170 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
174 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 181 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
182 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
186 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 178 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
179 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
183 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 178 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
179 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
183 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 219 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
220 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
224 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
|
| valid-mips64-el.txt | 15 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
16 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 17 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
|
| valid-mips1.txt | 74 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 18 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips4.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/valgrind/coregrind/m_gdbserver/ |
| valgrind-low-mips32.c | 181 && (rs == 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
|
| valgrind-low-mips64.c | 182 && (rs == 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
|
| /art/disassembler/ |
| disassembler_mips.cc | 233 { kITypeMask | (0x3e3 << 16), (17 << kOpcodeShift) | (8 << 21) | (1 << 16), "bc1t", "cB" },
506 case 'c': // Floating-point condition code flag in bc1f/bc1t and movf/movt.
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4.txt | 151 0x45 0x01 0x00 0x01 # CHECK: bc1t 8
155 0x45 0x05 0x00 0x00 # CHECK: bc1t $fcc1, 4
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 19 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
20 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
