| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 516 Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC ||
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| valid.txt | 43 0xe4 0x83 0x00 0x08 # CHECK: bgec $3, $4, 16
|
| /art/compiler/utils/mips/ |
| assembler_mips.cc | 944 void MipsAssembler::Bgec(Register rs, Register rt, uint16_t imm16) {
[all...] |
| assembler_mips.h | 336 void Bgec(Register rs, Register rt, uint16_t imm16); // R6
[all...] |
| assembler_mips32r6_test.cc | 888 // MipsAssembler::Bgec
|
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 823 TEST_F(AssemblerMIPS64Test, Bgec) {
824 BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgec, "Bgec");
[all...] |
| /external/v8/src/mips/ |
| disasm-mips.cc | [all...] |
| simulator-mips.cc | [all...] |
| macro-assembler-mips.cc | [all...] |
| assembler-mips.cc | 1314 void Assembler::bgec(Register rs, Register rt, int16_t offset) { function in class:v8::Assembler
[all...] |
| /external/v8/src/mips64/ |
| disasm-mips64.cc | [all...] |
| macro-assembler-mips64.cc | [all...] |
| simulator-mips64.cc | [all...] |
| assembler-mips64.cc | 1300 void Assembler::bgec(Register rs, Register rt, int16_t offset) { function in class:v8::internal::Assembler
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | [all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips64.S | 38 * idioms, which should translate into bgec and bltc respectively with swapped
43 bgec \rreg, \lreg, \target
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mips-opc.c | [all...] |
