| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| Lan91xDxeHw.h | 94 #define EPHSR_16COL BIT4
120 #define RPCR_LS2B BIT4
146 #define CTR_RESERVED (BIT12 | BIT9 | BIT4)
187 #define IST_RX_OVRN BIT4
259 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsSata.h | 73 #define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
87 #define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
133 #define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4
195 #define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
204 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
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| PchRegsSmbus.h | 60 #define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
81 #define B_PCH_SMBUS_FAIL BIT4 // Failed
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| PchRegsSpi.h | 50 #define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size
81 #define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
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| PchRegsPcie.h | 81 #define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
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| /external/libutf/ |
| rune.c | 25 Bit4 = 3,
32 T4 = ((1<<(Bit4+1))-1) ^ 0xFF, /* 1111 0000 */
38 Rune4 = (1<<(Bit4+3*Bitx))-1,
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| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530Gpmc.h | 36 #define WRITEPROTECT_HIGH BIT4
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| Omap3530Dma.h | 113 #define DMA4_CSR_LAST BIT4
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| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Gpmc.h | 36 #define WRITEPROTECT_HIGH BIT4
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| Omap3530Dma.h | 113 #define DMA4_CSR_LAST BIT4
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| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioBlk.h | 53 #define VIRTIO_BLK_F_GEOMETRY BIT4
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 112 #define BIT4 0x00000010
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| I2CLibPei.h | 28 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable
114 #define I2C_INTR_TX_EMPTY BIT4
139 #define STAT_RFF BIT4 // RX FIFO is completely full
178 #define I2C_INTR_TX_EMPTY BIT4
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 301 isbM32m(MCU, DPMC1, 2 << 4, BIT5|BIT4);
558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
588 isbM32m(DDRPHY, (B0VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
589 isbM32m(DDRPHY, (B1VREFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x03<<2)|(0x0<<1)|(0x0<<0)), ((BIT7|BIT6|BIT5|BIT4|BIT3|BIT2)|BIT1|BIT0)); // Internal Vref Code, Enable#, Ext_or_Int (1=Ext)
590 isbM32m(DDRPHY, (B0RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (0), (BIT4)); // Per-Bit De-Skew Enable
591 isbM32m(DDRPHY, (B1RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (0), (BIT4)); // Per-Bit De-Skew Enable
600 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/ |
| InitPeripherals.c | 99 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4);
102 } while ((Value & BIT4) == 0);
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/ |
| NorFlashDxe.h | 59 #define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 65 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
84 #define XHC_PORTSC_RESET BIT4 // Port Reset
101 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 87 #define MCI_STATUS_CMD_TX_UNDERRUN BIT4
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 65 #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb
95 #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity
105 #define INSTS_RSFF BIT4 // Rx Status FIFO full
162 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
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| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/ |
| IdeData.h | 289 #define TIME1 BIT4
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| /device/linaro/bootloader/edk2/SecurityPkg/Include/Library/ |
| Tcg2PhysicalPresenceLib.h | 30 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_ON BIT4
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| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| ArmV7Mmu.h | 21 #define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
22 #define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
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| /device/linaro/bootloader/edk2/OvmfPkg/QemuVideoDxe/ |
| VbeShim.c | 197 // bit4: set if graphics mode, clear if text mode
201 VbeModeInfo->ModeAttr = BIT7 | BIT5 | BIT4 | BIT3 | BIT1 | BIT0;
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| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Dxe/PlatformInit/ |
| PlatformConfig.c | 92 // Set "Pin Direction" bit4 and bit5 as outputs
107 // Lower GPORT3 bit4 and bit5 to Vss
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| I2cRegs.h | 51 #define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addressing (1)
53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
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