1 /** @file 2 I2C PEI Lib Instance. 3 4 Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #ifndef I2C_PEI_REGS_H 16 #define I2C_PEI_REGS_H 17 18 #include "PiPei.h" 19 20 #define R_PCH_LPC_PMC_BASE 0x44 21 #define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00 22 #define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register 23 #define PCIEX_BASE_ADDRESS 0xE0000000 24 #define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15) 25 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI Disable 26 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART #2 Disable 27 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART #1 Disable 28 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable 29 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable 30 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable 31 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable 32 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable 33 34 35 #define DEFAULT_PCI_BUS_NUMBER_PCH 0 36 37 #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command 38 #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA 39 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA 40 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List 41 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status 42 #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable 43 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable 44 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable 45 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable 46 47 #define R_PCH_LPSS_I2C_BAR 0x10 // BAR 48 #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address 49 #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator 50 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable 51 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type 52 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space 53 54 #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1 55 #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address 56 #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator 57 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable 58 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type 59 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space 60 61 #define NUM_RETRIES 0xFFFF 62 63 // 64 // LPIO I2C Module Memory Space Registers 65 // 66 #define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset 67 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset 68 #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset 69 70 #define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters 71 72 #define bit(a) 1 << (a) 73 74 // 75 // MMIO Register Definitions 76 // 77 78 #define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K 79 80 #define R_IC_CON ( 0x00) // I2C Control 81 #define B_IC_RESTART_EN BIT5 82 #define B_IC_SLAVE_DISABLE BIT6 83 #define V_SPEED_STANDARD 0x02 84 #define V_SPEED_FAST 0x04 85 #define V_SPEED_HIGH 0x06 86 #define B_MASTER_MODE BIT0 87 88 #define R_IC_TAR ( 0x04) // I2C Target Address 89 #define IC_TAR_10BITADDR_MASTER BIT12 90 91 #define R_IC_SAR ( 0x08) // I2C Slave Address 92 #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address 93 #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command 94 95 #define B_READ_CMD BIT8 // 1 = read, 0 = write 96 #define B_CMD_STOP BIT9 // 1 = STOP 97 #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN 98 99 #define V_WRITE_CMD_MASK ( 0xFF) 100 101 #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count 102 #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count 103 #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count 104 #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count 105 #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count 106 #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count 107 #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status 108 #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask 109 #define I2C_INTR_GEN_CALL BIT11 // General call received 110 #define I2C_INTR_START_DET BIT10 111 #define I2C_INTR_STOP_DET BIT9 112 #define I2C_INTR_ACTIVITY BIT8 113 #define I2C_INTR_TX_ABRT BIT6 // Set on NACK 114 #define I2C_INTR_TX_EMPTY BIT4 115 #define I2C_INTR_TX_OVER BIT3 116 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold 117 #define I2C_INTR_RX_OVER BIT1 118 #define I2C_INTR_RX_UNDER BIT0 119 #define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status 120 #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold 121 #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold 122 #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts 123 #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt 124 #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt 125 #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt 126 #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt 127 #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt 128 #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt 129 #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt 130 #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt 131 #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt 132 #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt 133 #define R_IC_ENABLE ( 0x6C) // I2C Enable 134 #define R_IC_STATUS ( 0x70) // I2C Status 135 136 #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits 137 138 #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status. 139 #define STAT_RFF BIT4 // RX FIFO is completely full 140 #define STAT_RFNE BIT3 // RX FIFO is not empty 141 #define STAT_TFE BIT2 // TX FIFO is completely empty 142 #define STAT_TFNF BIT1 // TX FIFO is not full 143 144 #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register 145 #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register 146 #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register 147 #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register 148 #define R_IC_DMA_CR ( 0x88) // DMA Control Register 149 #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level 150 #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level 151 #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register 152 #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register 153 #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register 154 #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register 155 #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID 156 #define R_IC_COMP_TYPE ( 0xFC) // Component Type 157 158 #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD 159 #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4 160 #define I2C_FS_SCL_HCNT_VALUE_100M 0x54 161 #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a 162 #define I2C_HS_SCL_HCNT_VALUE_100M 0x7 163 #define I2C_HS_SCL_LCNT_VALUE_100M 0xE 164 165 // 166 // FIFO write workaround value. 167 // 168 #define FIFO_WRITE_DELAY 2 169 #define IC_TAR_10BITADDR_MASTER BIT12 170 #define FIFO_SIZE 32 171 #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status 172 #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask 173 #define I2C_INTR_GEN_CALL BIT11 // General call received 174 #define I2C_INTR_START_DET BIT10 175 #define I2C_INTR_STOP_DET BIT9 176 #define I2C_INTR_ACTIVITY BIT8 177 #define I2C_INTR_TX_ABRT BIT6 // Set on NACK 178 #define I2C_INTR_TX_EMPTY BIT4 179 #define I2C_INTR_TX_OVER BIT3 180 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold 181 #define I2C_INTR_RX_OVER BIT1 182 #define I2C_INTR_RX_UNDER BIT0 183 184 /** 185 Programe all I2C controllers on LPSS. 186 187 I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc.. 188 189 @param VOID 190 191 @return EFI_SUCCESS 192 **/ 193 EFI_STATUS 194 ProgramPciLpssI2C ( 195 VOID 196 ); 197 198 /** 199 Reads a Byte from I2C Device. 200 201 @param I2cControllerIndex I2C Bus no to which the I2C device has been connected 202 @param SlaveAddress Device Address from which the byte value has to be read 203 @param Offset Offset from which the data has to be read 204 @param *Byte Address to which the value read has to be stored 205 @param Start Whether a RESTART is issued before the byte is sent or received 206 @param End Whether STOP is generated after a data byte is sent or received 207 208 @return EFI_SUCCESS If the byte value has been successfully read 209 @return EFI_DEVICE_ERROR Operation Failed, Device Error 210 **/ 211 EFI_STATUS 212 ByteReadI2CBasic( 213 IN UINT8 I2cControllerIndex, 214 IN UINT8 SlaveAddress, 215 IN UINTN ReadBytes, 216 OUT UINT8 *ReadBuffer, 217 IN UINT8 Start, 218 IN UINT8 End 219 ); 220 221 /** 222 Writes a Byte to I2C Device. 223 224 @param I2cControllerIndex I2C Bus no to which the I2C device has been connected 225 @param SlaveAddress Device Address from which the byte value has to be written 226 @param Offset Offset from which the data has to be read 227 @param *Byte Address to which the value written is stored 228 @param Start Whether a RESTART is issued before the byte is sent or received 229 @param End Whether STOP is generated after a data byte is sent or received 230 231 @return EFI_SUCCESS IF the byte value has been successfully written 232 @return EFI_DEVICE_ERROR Operation Failed, Device Error 233 **/ 234 EFI_STATUS 235 ByteWriteI2CBasic( 236 IN UINT8 I2cControllerIndex, 237 IN UINT8 SlaveAddress, 238 IN UINTN WriteBytes, 239 IN UINT8 *WriteBuffer, 240 IN UINT8 Start, 241 IN UINT8 End 242 ); 243 244 /** 245 Reads a Byte from I2C Device. 246 247 @param I2cControllerIndex I2C Bus no to which the I2C device has been connected 248 @param SlaveAddress Device Address from which the byte value has to be read 249 @param Offset Offset from which the data has to be read 250 @param ReadBytes Number of bytes to be read 251 @param *ReadBuffer Address to which the value read has to be stored 252 253 @return EFI_SUCCESS IF the byte value has been successfully read 254 @return EFI_DEVICE_ERROR Operation Failed, Device Error 255 **/ 256 EFI_STATUS 257 ByteReadI2C( 258 IN UINT8 I2cControllerIndex, 259 IN UINT8 SlaveAddress, 260 IN UINT8 Offset, 261 IN UINTN ReadBytes, 262 OUT UINT8 *ReadBuffer 263 ); 264 265 /** 266 Writes a Byte to I2C Device. 267 268 @param I2cControllerIndex I2C Bus no to which the I2C device has been connected 269 @param SlaveAddress Device Address from which the byte value has to be written 270 @param Offset Offset from which the data has to be written 271 @param WriteBytes Number of bytes to be written 272 @param *Byte Address to which the value written is stored 273 274 @return EFI_SUCCESS IF the byte value has been successfully read 275 @return EFI_DEVICE_ERROR Operation Failed, Device Error 276 **/ 277 EFI_STATUS 278 ByteWriteI2C( 279 IN UINT8 I2cControllerIndex, 280 IN UINT8 SlaveAddress, 281 IN UINT8 Offset, 282 IN UINTN WriteBytes, 283 IN UINT8 *WriteBuffer 284 ); 285 286 #endif 287
