| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 163 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
247 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
249 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 98 if (Addr.getOpcode() == ISD::ADD) {
119 if (Addr.getOpcode() == ISD::ADD) {
140 if (Addr.getOpcode() == ISD::ADD) {
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.s | 427 ADD DCval,DCval,#32
449 ADD pPredTemp,pPredTemp,predstep ;// Increment pPred ptr
459 QADD16 sum2,DeltaVal2,PredVal2 ;// Add and saturate to 16 bits
470 ADD pDstTemp,pDstTemp,dstStep ;// Increment pDst ptr
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/s390x/ |
| asmz.go | [all...] |
| /prebuilts/go/darwin-x86/src/runtime/ |
| sys_plan9_arm.s | 174 ADD.HS $1,R6 // sec += 1
262 ADD $4,R13,R5
305 ADD $1, R2
|
| rt0_linux_arm64.s | 9 ADD $8, RSP, R1 // argv
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/s390x/ |
| asmz.go | [all...] |
| /prebuilts/go/linux-x86/src/runtime/ |
| sys_plan9_arm.s | 174 ADD.HS $1,R6 // sec += 1
262 ADD $4,R13,R5
305 ADD $1, R2
|
| rt0_linux_arm64.s | 9 ADD $8, RSP, R1 // argv
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metafpu21ext.d | 81 .*: f1008821 FD ADD FX\.0,FX\.2,FX\.4
82 .*: f1184001 F ADD FX\.3,FX\.1,FX\.0
83 .*: f1310441 FL ADD FX\.6,FX\.4,FX\.2
84 .*: f10088a1 FDI ADD FX\.0,FX\.2,FX\.4
85 .*: f1184081 FI ADD FX\.3,FX\.1,FX\.0
86 .*: f13104c1 FLI ADD FX\.6,FX\.4,FX\.2
|
| /bionic/libc/include/arpa/ |
| nameser_compat.h | 119 #define ADD ns_uop_add
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| PlainInsn.java | 132 opcode = RegOps.ADD;
|
| /external/eigen/unsupported/test/ |
| autodiff.cpp | 261 typedef AutoDiffScalar<VectorAD> ADD;
262 typedef Matrix<ADD,Eigen::Dynamic,1> VectorADD;
286 ADD y = sin(AD(s3)*x(0) + AD(s4)*x(1));
295 ADD z = x(0)*x(1);
|
| /external/libchrome/base/metrics/ |
| sample_map.cc | 119 sample_counts_[min] += (op == HistogramSamples::ADD) ? count : -count;
|
| /external/libhevc/decoder/arm64/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 159 ADD x7,x0,x6 //// luma_next_row = luma + luma_stride
160 ADD x8,x2,x9,LSL #2 //// rgb_next_row = rgb + rgb_stride
500 ADD x0,x7,x10 //// luma = luma_next + offset
501 ADD x2,x8,x14,LSL #2 //// rgb = rgb_next + offset
503 ADD x7,x0,x3 //// luma_next = luma + width
504 ADD x8,x2,x3,LSL #2 //// rgb_next_row = rgb + width
506 ADD x1,x1,x11 //// adjust u pointer
507 //ADD x2,x2,x12 @// adjust v pointer
509 ADD x7,x7,x10 //// luma_next = luma + width + offset (because of register crunch)
510 ADD x8,x8,x14,LSL #2 //// rgb_next_row = rgb + width + offse
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Syn_filt_32_opt.s | 46 ADD r7, r3, #4 @ 4 + Q_new
146 ADD r14, r14, r7, LSL #1 @ L_tmp += (exc[i] * a0) << 1
205 ADD r6, r12, r12 @ r12 << 1
215 ADD r8, r8, #1
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.S | 32 ADD r12,r0,r1,LSL #2
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| omxVCM4P2_QuantInvInter_I_s.s | 119 ADD doubleQP,QP,QP ;// doubleQP= 2*QP
|
| /frameworks/base/tests/HwAccelerationTest/src/com/android/test/hwui/ |
| FramebufferBlendActivity.java | 81 drawBlendedBitmap(canvas, PorterDuff.Mode.ADD);
|
| /frameworks/compile/mclinker/include/mcld/Script/ |
| BinaryOp.h | 62 IntOperand* BinaryOp<Operator::ADD>::eval(const Module&,
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/arpa/ |
| nameser_compat.h | 128 #define ADD ns_uop_add
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/arpa/ |
| nameser_compat.h | 128 #define ADD ns_uop_add
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeTILEGX_64.c | 391 #define ADD(dst, srca, srcb) \
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| ARMOps.go | 132 {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
133 {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32"}, // arg0 + auxInt
157 {name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true}, // arg0 + arg1, set carry flag
158 {name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag
207 {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt
208 {name: "ADDshiftRL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift
209 {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, signed shift
243 {name: "ADDSshiftLL", argLength: 2, reg: gp21carry, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt, set carry flag
244 {name: "ADDSshiftRL", argLength: 2, reg: gp21carry, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift, set carry fla
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| ARMOps.go | 132 {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
133 {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32"}, // arg0 + auxInt
157 {name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true}, // arg0 + arg1, set carry flag
158 {name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag
207 {name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt
208 {name: "ADDshiftRL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift
209 {name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, signed shift
243 {name: "ADDSshiftLL", argLength: 2, reg: gp21carry, asm: "ADD", aux: "Int32"}, // arg0 + arg1<<auxInt, set carry flag
244 {name: "ADDSshiftRL", argLength: 2, reg: gp21carry, asm: "ADD", aux: "Int32"}, // arg0 + arg1>>auxInt, unsigned shift, set carry fla
[all...] |
