| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 104 case ISD::ADD:
457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
620 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
[all...] |
| LegalizeDAG.cpp | 438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
666 // Add the offset to the index.
669 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
[all...] |
| DAGCombiner.cpp | 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 67 .addImm(LPAC::ADD);
86 .addImm(LPAC::ADD);
754 // and with add as ALU op.
758 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 109 ADD $pSrc, $pSrc, $srcStep
112 ADD $pSrc, $pSrc, $srcStep
175 ADD $pSrc, $pSrc, $srcStep
693 QADD16 tmp1, tmp1, tmp3 ;// Add and saturate to 16 bits
|
| /frameworks/base/services/net/java/android/net/apf/ |
| ApfGenerator.java | 25 * Call add*() functions to add instructions to the program, then call
47 ADD(7), // Add, e.g. "add R0,5"
377 mInstructions.add(instruction);
403 * Add an unconditional jump instruction to the end of the program.
413 * Add an instruction to the end of the program to load the byte at offset {@code offset}
424 * Add an instruction to the end of the program to load 16-bits at offset {@code offset}
435 * Add an instruction to the end of the program to load 32-bits at offset {@code offset
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metacore21.d | 12 .*: 0001de01 ADD D0Re0,D0\.7,D1\.7
13 .*: 00380e01 ADD D0\.7,D0Re0,A1\.7
14 .*: 0039c000 ADD D0\.7,D0\.7,D0Re0
15 .*: 0039fe01 ADD D0\.7,D0\.7,A0\.7
16 .*: 01001e01 ADD D1Re0,D1Re0,D0\.7
17 .*: 0101ce01 ADD D1Re0,D1\.7,A1\.7
18 .*: 01380201 ADD D1\.7,D1Re0,A1LbP
19 .*: 01383201 ADD D1\.7,D1Re0,A0FrP
20 .*: 0139e001 ADD D1\.7,D1\.7,RD
148 .*: 06001fea ADD PC,D0Re0,#0x7
[all...] |
| metacore21.s | 4 ADD D0Re0,D0.7,D1.7
5 ADD D0.7,D0Re0,A1.7
6 ADD D0.7,D0.7,D0Re0
7 ADD D0.7,D0.7,A0.7
8 ADD D1Re0,D1Re0,D0.7
9 ADD D1Re0,D1.7,A1.7
10 ADD D1.7,D1Re0,A1LbP
11 ADD D1.7,D1Re0,A0FrP
12 ADD D1.7,D1.7,RD
140 ADD PC,D0Re0,#0x7
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nios2r1.h | 263 #define MATCH_R1_ADD MATCH_R1_OPX0 (ADD)
389 #define MATCH_R1_MOV MATCH_R1_OPX (ADD, 0, 0, 0)
409 #define MATCH_R1_NOP MATCH_R1_OPX (ADD, 0, 0, 0)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 281 // Add the flag if we have it.
360 // Add the flag if we have it.
831 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
[all...] |
| SparcISelDAGToDAG.cpp | 89 if (Addr.getOpcode() == ISD::ADD) {
128 if (Addr.getOpcode() == ISD::ADD) {
302 // Add the new register node and skip the original two GPRs.
|
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 211 ADD(AL, 0, parts.count.reg, parts.count.reg,
381 ADD(AL, 0, tx, tx, reg_imm(ty, LSL, GGL_DITHER_ORDER_SHIFT));
434 ADD(AL, 0, Rs, Rs, reg_imm(parts.count.reg, LSR, 16));
655 ADD(AL, 0, c, c, dx);
796 ADD(AL, 0, parts.z.reg, parts.z.reg, dzdx);
809 ADD(AL, 0, f, f, dfdx);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 164 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
204 case ISD::ADD: {
418 case ISD::ADD:
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_state_init.c | 221 #define CHECK( NM, FLAG, ADD ) \
226 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
229 #define TCL_CHECK( NM, FLAG, ADD ) \
233 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
236 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
240 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
243 #define VP_CHECK( NM, FLAG, ADD ) \
248 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 169 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
209 case ISD::ADD: {
418 case ISD::ADD:
|
| /external/v8/src/arm64/ |
| instrument-arm64.cc | 69 {"Add/Sub DP", Gauge},
243 static Counter* add_sub_counter = GetCounter("Add/Sub DP");
245 (instr->Mask(AddSubOpMask) == ADD)) &&
467 static Counter* counter = GetCounter("Add/Sub DP");
475 static Counter* add_sub_counter = GetCounter("Add/Sub DP");
477 (instr->Mask(AddSubOpMask) == ADD)) &&
489 static Counter* counter = GetCounter("Add/Sub DP");
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| opnames.go | 15 OADD: "ADD",
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 13 "ADD",
|
| /prebuilts/go/darwin-x86/src/cmd/vet/ |
| unsafeptr.go | 92 case token.ADD, token.SUB, token.AND_NOT:
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| sys_nacl_arm.s | 233 ADD.S R2, R0
279 ADD $64, R1
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| opnames.go | 15 OADD: "ADD",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 13 "ADD",
|
| /prebuilts/go/linux-x86/src/cmd/vet/ |
| unsafeptr.go | 92 case token.ADD, token.SUB, token.AND_NOT:
|
| /prebuilts/go/linux-x86/src/runtime/ |
| sys_nacl_arm.s | 233 ADD.S R2, R0
279 ADD $64, R1
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 321 // a got and then add the offset.
325 // If the code is position independent we will have to add a base register.
[all...] |
