| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/ |
| checkbce.go | 18 if v.Op == OpIsInBounds || v.Op == OpIsSliceInBounds {
19 f.Config.Warnl(v.Line, "Found %v", v.Op)
|
| deadstore.go | 26 if v.Op == OpPhi {
32 if v.Op == OpSelect1 {
33 // Use the args of the tuple-generating op.
39 if v.Op != OpStore && v.Op != OpZero && v.Op != OpVarDef && v.Op != OpVarKill {
86 if v.Op == OpStore || v.Op == OpZero {
88 if v.Op == OpStore
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/ |
| checkbce.go | 18 if v.Op == OpIsInBounds || v.Op == OpIsSliceInBounds {
19 f.Config.Warnl(v.Line, "Found %v", v.Op)
|
| deadstore.go | 26 if v.Op == OpPhi {
32 if v.Op == OpSelect1 {
33 // Use the args of the tuple-generating op.
39 if v.Op != OpStore && v.Op != OpZero && v.Op != OpVarDef && v.Op != OpVarKill {
86 if v.Op == OpStore || v.Op == OpZero {
88 if v.Op == OpStore
[all...] |
| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| TensorReductionCuda.h | 263 template <typename Op>
264 __global__ void ReductionCleanupKernelHalfFloat(Op& reducer, half* output, half2* scratch) {
273 template <typename Self, typename Op, typename OutputType, bool PacketAccess, typename Enabled = void>
275 static void run(const Self&, Op&, const GpuDevice&, OutputType*, typename Self::Index) {
281 template <typename Self, typename Op, typename OutputType, bool PacketAccess>
283 Self, Op, OutputType, PacketAccess,
288 static void run(const Self& self, Op& reducer, const GpuDevice& device, OutputType* output, typename Self::Index num_coeffs) {
300 LAUNCH_CUDA_KERNEL((FullReductionKernel<block_size, num_per_thread, Self, Op, Index>),
306 template <typename Self, typename Op>
307 struct FullReductionLauncher<Self, Op, Eigen::half, false>
[all...] |
| TensorReductionSycl.h | 102 template <typename Self, typename Op, bool Vectorizable>
103 struct FullReducer<Self, Op, const Eigen::SyclDevice, Vectorizable> {
108 static void run(const Self& self, Op& reducer, const Eigen::SyclDevice& dev, CoeffReturnType* output) {
144 Op functor = reducer;
156 const auto device_self_expr= TensorReductionOp<Op, Dims, decltype(device_expr.expr) ,MakeGlobalPointer>(device_expr.expr, dims, functor);
164 tmp_global_accessor.get_pointer()[globalid]=InnerMostDimReducer<decltype(device_self_evaluator), Op, false>::reduce(device_self_evaluator, red_factor*globalid, red_factor, const_cast<Op&>(functor));
170 tmp_global_accessor.get_pointer()[globalid]+=InnerMostDimReducer<decltype(device_self_evaluator), Op, false>::reduce(device_self_evaluator, red_factor*(rng), remaining, const_cast<Op&>(functor));
181 template <typename Self, typename Op>
[all...] |
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 568 auto Op = make_unique<LanaiOperand>(TOKEN);
569 Op->Tok.Data = Str.data();
570 Op->Tok.Length = Str.size();
571 Op->StartLoc = Start;
572 Op->EndLoc = Start;
573 return Op;
578 auto Op = make_unique<LanaiOperand>(REGISTER);
579 Op->Reg.RegNum = RegNum;
580 Op->StartLoc = Start;
581 Op->EndLoc = End
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 201 const MCOperand &Op = MI->getOperand(OpNo);
202 if (Op.isReg()) {
203 unsigned Reg = Op.getReg();
205 } else if (Op.isImm()) {
206 O << '#' << Op.getImm();
208 assert(Op.isExpr() && "unknown operand kind in printOperand");
211 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
219 O << *Op.getExpr();
278 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
280 const MCOperand &MO1 = MI->getOperand(Op);
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/Bitcode/ |
| BitstreamWriter.h | 260 /// record. This is a no-op, since the abbrev specifies the literal to use.
262 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
263 assert(Op.isLiteral() && "Not a literal");
266 assert(V == Op.getLiteralValue() &&
273 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
274 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
277 switch (Op.getEncoding()) {
280 if (Op.getEncodingData())
281 Emit((unsigned)V, (unsigned)Op.getEncodingData());
284 if (Op.getEncodingData()
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
263 switch (Op.getOpcode()) {
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
271 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
272 EVT VT = Op.getValueType();
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | 491 SDValue Op = OrigOp;
493 AnalyzeNewValue(Op); // Op may morph.
495 if (Op.getNode()->getNodeId() == Processed)
500 NewOps.push_back(Op);
501 } else if (Op != OrigOp) {
504 NewOps.push_back(Op);
750 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
752 TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
756 SDValue &OpEntry = PromotedIntegers[Op];
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 62 MCInstBuilder &addOperand(const MCOperand &Op) {
63 Inst.addOperand(Op);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 140 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
141 switch (Op) {
153 setOperationAction(Op, VT, Custom);
156 setOperationAction(Op, VT, Expand);
538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
542 if (VT == MVT::i1 && Op == ISD::SETCC)
545 return TargetLowering::isTypeDesirableForOp(Op, VT);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXReplaceImageHandles.cpp | 44 void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
45 bool findIndexForHandle(MachineOperand &Op, MachineFunction &MF,
125 replaceImageHandle(MachineOperand &Op, MachineFunction &MF) {
127 if (findIndexForHandle(Op, MF, Idx)) {
128 Op.ChangeToImmediate(Idx);
133 findIndexForHandle(MachineOperand &Op, MachineFunction &MF, unsigned &Idx) {
137 assert(Op.isReg() && "Handle is not in a reg?");
140 MachineInstr &TexHandleDef = *MRI.getVRegDef(Op.getReg());
|
| /external/skia/src/gpu/instanced/ |
| GLInstancedRendering.h | 36 std::unique_ptr<Op> makeOp(GrPaint&& paint) override;
39 void onDraw(const GrPipeline&, const InstanceProcessor&, const Op*) override;
|
| /prebuilts/go/darwin-x86/src/net/ |
| error_posix_test.go | 22 {&OpError{Op: "op", Err: syscall.EADDRNOTAVAIL}, true},
23 {&OpError{Op: "op", Err: &os.SyscallError{Syscall: "syscall", Err: syscall.EADDRNOTAVAIL}}, true},
27 {&OpError{Op: "op", Err: syscall.EINVAL}, false},
28 {&OpError{Op: "op", Err: &os.SyscallError{Syscall: "syscall", Err: syscall.EINVAL}}, false},
|
| /prebuilts/go/darwin-x86/test/fixedbugs/issue4932.dir/ |
| foo.go | 7 type Op struct{}
|
| /prebuilts/go/linux-x86/src/net/ |
| error_posix_test.go | 22 {&OpError{Op: "op", Err: syscall.EADDRNOTAVAIL}, true},
23 {&OpError{Op: "op", Err: &os.SyscallError{Syscall: "syscall", Err: syscall.EADDRNOTAVAIL}}, true},
27 {&OpError{Op: "op", Err: syscall.EINVAL}, false},
28 {&OpError{Op: "op", Err: &os.SyscallError{Syscall: "syscall", Err: syscall.EINVAL}}, false},
|
| /prebuilts/go/linux-x86/test/fixedbugs/issue4932.dir/ |
| foo.go | 7 type Op struct{}
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 40 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
50 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/skia/include/effects/ |
| SkMorphologyImageFilter.h | 32 enum Op {
37 virtual Op op() const = 0;
66 Op op() const override { return kDilate_Op; }
88 Op op() const override { return kErode_Op; }
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.h | 37 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.h | 47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
52 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
96 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
| /external/libcxx/test/std/experimental/filesystem/class.directory_entry/directory_entry.obs/ |
| comparisons.pass.cpp | 30 #define CHECK_OP(Op) \
31 static_assert(std::is_same<decltype(ce. operator Op (ce)), bool>::value, ""); \
32 static_assert(noexcept(ce.operator Op (ce)), "Operation must be noexcept" )
|
| /external/llvm/lib/IR/ |
| IntrinsicInst.cpp | 36 Value *Op = getArgOperand(0);
37 if (AllowNullOp && !Op)
40 auto *MD = cast<MetadataAsValue>(Op)->getMetadata();
|
