| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 70 .addReg(SrcReg, getKillRegState(isKill));
123 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| TargetInstrInfo.cpp | 732 .addReg(RegX, getKillRegState(KillX))
733 .addReg(RegY, getKillRegState(KillY));
736 .addReg(RegA, getKillRegState(KillA))
737 .addReg(NewVR, getKillRegState(true));
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiMemAluCombiner.cpp | 261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 635 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
718 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
722 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
[all...] |
| AArch64FrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc)));
142 .addReg(SrcReg, getKillRegState(isKill))
157 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
|
| Thumb1FrameLowering.cpp | 601 MIB.addReg(Reg, getKillRegState(isKill));
|
| Thumb2SizeReduction.cpp | 570 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | 765 unsigned KillFlag = getKillRegState(KillSrc);
873 unsigned KillFlag = getKillRegState(isKill);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 174 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
216 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
247 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 398 .addReg(SrcReg, getKillRegState(KillSrc));
405 .addReg(SrcReg, getKillRegState(KillSrc));
411 .addReg(SrcReg, getKillRegState(KillSrc));
419 .addReg(SrcReg, getKillRegState(KillSrc));
441 .addReg(SrcReg, getKillRegState(KillSrc));
495 Builder.addReg(SrcReg, getKillRegState(KillSrc) | RegState::Implicit);
603 .addReg(SrcReg, getKillRegState(isKill)) // src
625 .addReg(SrcReg, getKillRegState(isKill)) // src
901 .addReg(SrcCond.getReg(), getKillRegState(SrcCond.isKill()))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 519 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
642 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 72 .addReg(SrcReg, getKillRegState(KillSrc))
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 321 MIB.addReg(Reg, getKillRegState(isKill));
|
| ARMFrameLowering.cpp | 599 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
603 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
[all...] |
| Thumb1RegisterInfo.cpp | 271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
|
| Thumb2SizeReduction.cpp | 456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 60 addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 473 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
486 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 125 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
|
