| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-a32-asrs.h | 38 0x55, 0x4e, 0xb0, 0xd1 // asrs le r4 r5 r14
41 0x5b, 0x5a, 0xb0, 0xa1 // asrs ge r5 r11 r10
44 0x59, 0x09, 0xb0, 0x91 // asrs ls r0 r9 r9
47 0x57, 0x82, 0xb0, 0xd1 // asrs le r8 r7 r2
50 0x5a, 0x1d, 0xb0, 0x01 // asrs eq r1 r10 r13
53 0x5c, 0x92, 0xb0, 0xd1 // asrs le r9 r12 r2
56 0x51, 0x65, 0xb0, 0x51 // asrs pl r6 r1 r5
59 0x5c, 0x16, 0xb0, 0xa1 // asrs ge r1 r12 r6
62 0x5c, 0xd3, 0xb0, 0x31 // asrs cc r13 r12 r3
65 0x54, 0x29, 0xb0, 0xc1 // asrs gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-t32-asrs.h | 38 0x59, 0xfa, 0x0b, 0xfc // asrs al r12 r9 r11
41 0x54, 0xfa, 0x0a, 0xf3 // asrs al r3 r4 r10
44 0x50, 0xfa, 0x0c, 0xf2 // asrs al r2 r0 r12
47 0x59, 0xfa, 0x0d, 0xf9 // asrs al r9 r9 r13
50 0x52, 0xfa, 0x04, 0xfb // asrs al r11 r2 r4
53 0x53, 0xfa, 0x07, 0xf7 // asrs al r7 r3 r7
56 0x56, 0xfa, 0x09, 0xfb // asrs al r11 r6 r9
59 0x57, 0xfa, 0x0b, 0xf8 // asrs al r8 r7 r11
62 0x5c, 0xfa, 0x0e, 0xfe // asrs al r14 r12 r14
65 0x55, 0xfa, 0x08, 0xf8 // asrs al r8 r5 r
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-asr.ll | 5 ; CHECK: asrs r0, r1
|
| thumb2-asr2.ll | 5 ; CHECK: asrs r0, r0, #17
|
| thumb2-lsr3.ll | 14 ; CHECK: asrs.w r1, r1, #1
|
| thumb2-shifter.ll | 74 ; A8: asrs r1, r2
78 ; SWIFT-NOT: asrs
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-asr.ll | 5 ; CHECK: asrs r0, r1
|
| thumb2-asr2.ll | 5 ; CHECK: asrs r0, r0, #17
|
| thumb2-lsr3.ll | 14 ; CHECK: asrs.w r1, r1, #1
|
| /external/llvm/test/CodeGen/Thumb/ |
| 2012-04-26-M0ISelBug.ll | 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
|
| ldr_ext.ll | 27 ; V5: asrs
39 ; V5: asrs
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat.s | 18 shift asr asrls asrs asrlss
|
| tcompat.d | 25 0+38 <[^>]*> e1b008c0 ? asrs r0, r0, #17
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| ldr_ext.ll | 27 ; V5: asrs
39 ; V5: asrs
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| thumb-diagnostics.s | 26 asrs r2, r3, #33
27 asrs r2, r3, #0
29 @ CHECK-ERRORS: asrs r2, r3, #33
32 @ CHECK-ERRORS: asrs r2, r3, #0
|
| /external/llvm/test/MC/ARM/ |
| thumb_rewrites.s | 77 asrs r0, r0, r1
78 @ CHECK: asrs r0, r1 @ encoding: [0x08,0x41]
|
| thumb2-narrow-dp.ll | 418 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
419 ASRS r0, r0, r1 // Should choose narrow
420 ASRS r0, r1, r0 // Should choose wide - not commutative
421 ASRS.W r3, r3, r1 // Explicitly wide
422 ASRS.W r1, r1, r1
424 ASRS r7, r7, r1 // Should use narrow
425 ASRS r8, r1, r8 // high registers so must use wide encoding
426 ASRS r8, r8, r1
427 ASRS r5, r8, r5
428 ASRS r5, r5, r
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| ldivmod.asm | 31 ASRS r4,r1,#1
|
| ldivmod.S | 34 asrs r4,r1,#1
|
| /external/valgrind/none/tests/arm/ |
| v6intARM.stdout.exp | 205 ASRS
206 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N
207 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C
208 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C
209 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C
210 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0xa0000000 N C
211 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0xa0000000 N C
212 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0xa0000000 N C
213 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0xa0000000 N C
214 asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0xa0000000 N C
[all...] |
| v6intARM.c | 305 printf("ASRS\n");
307 TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
308 TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
309 TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
310 TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
311 TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
312 TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
313 TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
314 TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
315 TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c)
[all...] |
| /external/elfutils/libebl/ |
| eblcorenotetypename.c | 55 KNOWNSTYPE (ASRS),
|
| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-rm-a32.json | 75 "Asrs", // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
|
| cond-rd-rn-operand-rm-t32.json | 125 "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
126 // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
|
| /external/llvm/test/CodeGen/ARM/ |
| thumb2-size-opt.ll | 16 ; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
25 ; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
|
