1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following forms: 28 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm>, <Rs> 29 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } 30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } 31 // 32 // Note that this test only covers the cases where the optional shift 33 // operand is not provided. The shift operands are tested in 34 // "cond-rd-rn-operand-rm-shift-amount-*-a32.json". 35 36 { 37 "mnemonics": [ 38 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 40 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 41 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 42 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 43 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 44 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 45 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 46 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 47 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 48 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 49 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 50 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 51 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 52 "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 53 "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 54 "Rsc", // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 55 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 56 "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 57 "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 58 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 59 // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 60 "Subs", // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 61 // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 62 63 "Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 64 "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 65 "Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 66 "Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 67 "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 68 "Uxtah", // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 69 70 // Shift instructions that alias to MOV. 71 // Note that we are not giving them a different input for their 72 // last operand since they are already tested in 73 // "cond-rd-operand-rn-shift-rs-a32.json". 74 "Asr", // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 75 "Asrs", // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 76 "Lsl", // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 77 "Lsls", // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 78 "Lsr", // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 79 "Lsrs", // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 80 "Ror", // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 81 "Rors" // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1 82 ], 83 "description": { 84 "operands": [ 85 { 86 "name": "cond", 87 "type": "Condition" 88 }, 89 { 90 "name": "rd", 91 "type": "AllRegistersButPC" 92 }, 93 { 94 "name": "rn", 95 "type": "AllRegistersButPC" 96 }, 97 { 98 "name": "op", 99 "wrapper": "Operand", 100 "operands": [ 101 { 102 "name": "rm", 103 "type": "AllRegistersButPC" 104 } 105 ] 106 } 107 ], 108 "inputs": [ 109 { 110 "name": "apsr", 111 "type": "NZCV" 112 }, 113 { 114 "name": "rd", 115 "type": "Register" 116 }, 117 { 118 "name": "rn", 119 "type": "Register" 120 }, 121 { 122 "name": "rm", 123 "type": "Register" 124 } 125 ] 126 }, 127 "test-files": [ 128 { 129 "type": "assembler", 130 "test-cases": [ 131 { 132 "name": "Operands", 133 "operands": [ 134 "cond", "rd", "rn", "rm" 135 ], 136 "operand-limit": 500 137 } 138 ] 139 }, 140 { 141 "type": "simulator", 142 "test-cases": [ 143 { 144 "name": "Condition", 145 "operands": [ 146 "cond" 147 ], 148 "inputs": [ 149 "apsr" 150 ] 151 }, 152 // Test combinations of registers values with rd == rn. 153 { 154 "name": "RdIsRn", 155 "operands": [ 156 "rd", "rn", "rm" 157 ], 158 "inputs": [ 159 "rd", "rn", "rm" 160 ], 161 "operand-filter": "rd == rn and rn != rm", 162 "operand-limit": 10, 163 "input-filter": "rd == rn", 164 "input-limit": 200 165 }, 166 // Test combinations of registers values with rd == rm. 167 { 168 "name": "RdIsRm", 169 "operands": [ 170 "rd", "rn", "rm" 171 ], 172 "inputs": [ 173 "rd", "rn", "rm" 174 ], 175 "operand-filter": "rd == rm and rn != rm", 176 "operand-limit": 10, 177 "input-filter": "rd == rm", 178 "input-limit": 200 179 }, 180 // Test combinations of registers values. 181 { 182 "name": "RdIsNotRnIsNotRm", 183 "operands": [ 184 "rd", "rn", "rm" 185 ], 186 "inputs": [ 187 "rd", "rn", "rm" 188 ], 189 "operand-filter": "rd != rn != rm", 190 "operand-limit": 10, 191 "input-limit": 200 192 } 193 ] 194 } 195 ] 196 } 197
