| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 198 bgeuc $2, $3, ext
199 bgeuc $2, $3, . + 4 + (-32768 << 2)
200 bgeuc $2, $3, . + 4 + (32767 << 2)
201 bgeuc $2, $3, 1f
202 bgeuc $3, $2, 1f
|
| r6-n32.d | 373 0+0448 <[^>]*> 18430000 bgeuc v0,v1,0000044c <[^>]*>
376 0+0450 <[^>]*> 18430000 bgeuc v0,v1,00000454 <[^>]*>
379 0+0458 <[^>]*> 18430000 bgeuc v0,v1,0000045c <[^>]*>
382 0+0460 <[^>]*> 18430000 bgeuc v0,v1,00000464 <[^>]*>
385 0+0468 <[^>]*> 18620000 bgeuc v1,v0,0000046c <[^>]*>
|
| r6.d | 372 0+0448 <[^>]*> 1843ffff bgeuc v0,v1,00000448 <[^>]*>
375 0+0450 <[^>]*> 18438000 bgeuc v0,v1,fffe0454 <[^>]*>
378 0+0458 <[^>]*> 18437fff bgeuc v0,v1,00020458 <[^>]*>
381 0+0460 <[^>]*> 1843ffff bgeuc v0,v1,00000460 <[^>]*>
384 0+0468 <[^>]*> 1862ffff bgeuc v1,v0,00000468 <[^>]*>
|
| r6-n64.d | 549 0+0448 <[^>]*> 18430000 bgeuc v0,v1,0+044c <[^>]*>
554 0+0450 <[^>]*> 18430000 bgeuc v0,v1,0+0454 <[^>]*>
559 0+0458 <[^>]*> 18430000 bgeuc v0,v1,0+045c <[^>]*>
564 0+0460 <[^>]*> 18430000 bgeuc v0,v1,0+0464 <[^>]*>
569 0+0468 <[^>]*> 18620000 bgeuc v1,v0,0+046c <[^>]*>
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 28 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
29 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
|
| valid-mips32r6.txt | 44 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
45 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 26 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
27 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
|
| valid-mips64r6.txt | 61 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
62 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid.s | 50 bgeuc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
56 bgeuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| valid.s | 46 bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40]
|
| /external/v8/src/mips/ |
| assembler-mips.h | 616 void bgeuc(Register rs, Register rt, int16_t offset);
617 inline void bgeuc(Register rs, Register rt, Label* L) {
618 bgeuc(rs, rt, shifted_branch_offset(L));
[all...] |
| constants-mips.h | 401 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 623 void bgeuc(Register rs, Register rt, int16_t offset);
624 inline void bgeuc(Register rs, Register rt, Label* L) {
625 bgeuc(rs, rt, shifted_branch_offset(L));
[all...] |
| constants-mips64.h | 384 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips32r6InstrInfo.td | 396 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
761 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
[all...] |
| MipsInstrInfo.cpp | 322 return Mips::BGEUC;
|
| MicroMips32r6InstrInfo.td | 60 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
282 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm,
[all...] |
| MipsSEInstrInfo.cpp | 516 Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC ||
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 42 bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40]
|
| invalid.s | 52 bgeuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 556 void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | [all...] |
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 25 bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x08]
[all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 211 { kITypeMask, 6 << kOpcodeShift, "bgeuc", "STB" },
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| valid.txt | 44 0xc0 0x83 0x00 0x08 # CHECK: bgeuc $3, $4, 16
|
