1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes microMIPSr6 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def brtarget21_mm : Operand<OtherVT> { 15 let EncoderMethod = "getBranchTarget21OpValueMM"; 16 let OperandType = "OPERAND_PCREL"; 17 let DecoderMethod = "DecodeBranchTarget21MM"; 18 let ParserMatchClass = MipsJumpTargetAsmOperand; 19 } 20 21 def brtarget26_mm : Operand<OtherVT> { 22 let EncoderMethod = "getBranchTarget26OpValueMM"; 23 let OperandType = "OPERAND_PCREL"; 24 let DecoderMethod = "DecodeBranchTarget26MM"; 25 let ParserMatchClass = MipsJumpTargetAsmOperand; 26 } 27 28 def brtargetr6 : Operand<OtherVT> { 29 let EncoderMethod = "getBranchTargetOpValueMMR6"; 30 let OperandType = "OPERAND_PCREL"; 31 let DecoderMethod = "DecodeBranchTargetMM"; 32 let ParserMatchClass = MipsJumpTargetAsmOperand; 33 } 34 35 //===----------------------------------------------------------------------===// 36 // 37 // Instruction Encodings 38 // 39 //===----------------------------------------------------------------------===// 40 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>; 41 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>; 42 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>; 43 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>; 44 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>; 45 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>; 46 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>; 47 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>; 48 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>; 49 class AUI_MMR6_ENC : AUI_FM_MMR6; 50 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; 51 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; 52 class BC16_MMR6_ENC : BC16_FM_MM16R6; 53 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>; 54 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>; 55 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; 56 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">; 57 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>; 58 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>; 59 class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111001>; 60 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>, 61 DecodeDisambiguates<"BlezGroupBranchMMR6">; 62 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110001>; 63 class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>, 64 DecodeDisambiguates<"BgtzGroupBranchMMR6">; 65 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>; 66 class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>; 67 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>; 68 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>; 69 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>, 70 MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">; 71 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>, 72 MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">; 73 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>, 74 MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">; 75 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>, 76 MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">; 77 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>; 78 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>; 79 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>; 80 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>; 81 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>; 82 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>; 83 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>; 84 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>; 85 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>; 86 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>; 87 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">; 88 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>; 89 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>; 90 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>; 91 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>; 92 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>; 93 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>; 94 class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>; 95 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>; 96 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>; 97 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>; 98 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>; 99 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>; 100 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>; 101 class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>; 102 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>; 103 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>; 104 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>; 105 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>; 106 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>; 107 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>; 108 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>; 109 class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>; 110 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>; 111 class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>; 112 class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>; 113 class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>; 114 class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>; 115 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>; 116 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; 117 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; 118 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; 119 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>; 120 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>; 121 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>; 122 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; 123 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>; 124 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>; 125 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>; 126 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; 127 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; 128 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>; 129 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>; 130 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>; 131 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>; 132 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>; 133 class SWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x9>; 134 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>; 135 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>; 136 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>; 137 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>; 138 class LB_MMR6_ENC : LB32_FM_MMR6; 139 class LBU_MMR6_ENC : LBU32_FM_MMR6; 140 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>; 141 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>; 142 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>; 143 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6; 144 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">; 145 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">; 146 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6; 147 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">; 148 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>; 149 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">; 150 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>; 151 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>; 152 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>; 153 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>; 154 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>; 155 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>; 156 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>; 157 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>; 158 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>; 159 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>; 160 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>; 161 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>; 162 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>; 163 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>; 164 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>; 165 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>; 166 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>; 167 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>; 168 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>; 169 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>; 170 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>; 171 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>; 172 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>; 173 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; 174 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>; 175 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>; 176 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; 177 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; 178 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; 179 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; 180 class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>; 181 class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>; 182 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; 183 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>; 184 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0, 185 0b11001100>; 186 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1, 187 0b11001100>; 188 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0, 189 0b11101100>; 190 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1, 191 0b11101100>; 192 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>; 193 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>; 194 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>; 195 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>; 196 class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>; 197 class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>; 198 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>; 199 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>; 200 class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>; 201 class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>; 202 class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>; 203 class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">; 204 class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">; 205 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6; 206 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6; 207 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16; 208 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6; 209 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>; 210 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16; 211 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16; 212 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; 213 class LI16_MMR6_ENC : LI_FM_MM16; 214 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; 215 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; 216 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; 217 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; 218 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; 219 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; 220 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>; 221 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>; 222 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>; 223 class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>; 224 class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>; 225 class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>; 226 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>; 227 class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>; 228 class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>; 229 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>; 230 class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>; 231 class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; 232 233 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, 234 RegisterOperand GPROpnd> 235 : BRANCH_DESC_BASE { 236 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 237 dag OutOperandList = (outs); 238 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 239 list<Register> Defs = [AT]; 240 } 241 242 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm, 243 GPR32Opnd> { 244 list<Register> Defs = [RA]; 245 } 246 247 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm, 248 GPR32Opnd> { 249 list<Register> Defs = [RA]; 250 } 251 252 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm, 253 GPR32Opnd> { 254 list<Register> Defs = [RA]; 255 } 256 257 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm, 258 GPR32Opnd> { 259 list<Register> Defs = [RA]; 260 } 261 262 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm, 263 GPR32Opnd> { 264 list<Register> Defs = [RA]; 265 } 266 267 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm, 268 GPR32Opnd> { 269 list<Register> Defs = [RA]; 270 } 271 272 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, 273 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 274 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 275 dag OutOperandList = (outs); 276 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 277 list<Register> Defs = [AT]; 278 } 279 280 class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_mm, 281 GPR32Opnd>; 282 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm, 283 GPR32Opnd>; 284 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_mm, 285 GPR32Opnd>; 286 class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_mm, 287 GPR32Opnd>; 288 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_mm, 289 GPR32Opnd>; 290 class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_mm, 291 GPR32Opnd>; 292 293 /// Floating Point Instructions 294 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; 295 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; 296 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; 297 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; 298 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; 299 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; 300 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; 301 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; 302 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; 303 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; 304 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; 305 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; 306 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; 307 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; 308 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; 309 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; 310 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; 311 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; 312 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; 313 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; 314 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; 315 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; 316 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; 317 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; 318 319 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; 320 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; 321 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; 322 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; 323 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; 324 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; 325 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; 326 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; 327 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; 328 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; 329 330 //===----------------------------------------------------------------------===// 331 // 332 // Instruction Descriptions 333 // 334 //===----------------------------------------------------------------------===// 335 336 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; 337 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>; 338 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; 339 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>; 340 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>; 341 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>; 342 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>; 343 344 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd> 345 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> { 346 dag InOperandList = (ins opnd:$offset); 347 dag OutOperandList = (outs); 348 string AsmString = !strconcat(instr_asm, "\t$offset"); 349 bit isBarrier = 1; 350 } 351 352 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> { 353 bit isCall = 1; 354 list<Register> Defs = [RA]; 355 } 356 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>; 357 358 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset), 359 !strconcat("bc16", "\t$offset"), [], 360 II_BC, FrmI>, 361 MMR6Arch<"bc16">, MicroMipsR6Inst16 { 362 let isBranch = 1; 363 let isTerminator = 1; 364 let isBarrier = 1; 365 let hasDelaySlot = 0; 366 let AdditionalPredicates = [RelocPIC]; 367 let Defs = [AT]; 368 } 369 370 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm> 371 : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> { 372 let isBranch = 1; 373 let isTerminator = 1; 374 let hasDelaySlot = 0; 375 let Defs = [AT]; 376 } 377 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">; 378 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">; 379 380 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>; 381 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>; 382 383 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 384 : MMR6Arch<instr_asm> { 385 dag OutOperandList = (outs GPROpnd:$rd); 386 dag InOperandList = (ins GPROpnd:$rt); 387 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 388 list<dag> Pattern = []; 389 } 390 391 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; 392 393 class BRK_MMR6_DESC : BRK_FT<"break">; 394 395 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd, 396 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { 397 dag OutOperandList = (outs); 398 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 399 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 400 list<dag> Pattern = []; 401 string DecoderMethod = "DecodeCacheOpMM"; 402 } 403 404 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>; 405 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>; 406 407 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, 408 RegisterOperand GPROpnd> : 409 CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, 410 GPROpnd> { 411 string DecoderMethod = "DecodePrefeOpMM"; 412 } 413 414 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>; 415 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>; 416 417 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, 418 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { 419 dag OutOperandList = (outs GPROpnd:$rt); 420 dag InOperandList = (ins MemOpnd:$addr); 421 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 422 string DecoderMethod = "DecodeLoadByte15"; 423 bit mayLoad = 1; 424 } 425 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>; 426 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>; 427 428 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, 429 RegisterOperand GPROpnd> 430 : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> { 431 let DecoderMethod = "DecodeLoadByte9"; 432 } 433 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>; 434 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>; 435 436 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 437 : MMR6Arch<instr_asm> { 438 dag OutOperandList = (outs GPROpnd:$rt); 439 dag InOperandList = (ins GPROpnd:$rs); 440 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 441 } 442 443 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>; 444 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>; 445 446 class EHB_MMR6_DESC : Barrier<"ehb">; 447 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>; 448 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>; 449 450 class ERET_MMR6_DESC : ER_FT<"eret">; 451 class DERET_MMR6_DESC : ER_FT<"deret">; 452 class ERETNC_MMR6_DESC : ER_FT<"eretnc">; 453 454 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO> 455 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), 456 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, 457 MMR6Arch<opstr>, MicroMipsR6Inst16 { 458 let isCall = 1; 459 let hasDelaySlot = 0; 460 let Defs = [RA]; 461 } 462 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>; 463 464 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 465 RegisterOperand GPROpnd> 466 : MMR6Arch<opstr> { 467 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 468 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 469 list<dag> Pattern = []; 470 bit isTerminator = 1; 471 bit hasDelaySlot = 0; 472 } 473 474 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 475 GPR32Opnd> { 476 bit isCall = 1; 477 list<Register> Defs = [RA]; 478 } 479 480 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, 481 GPR32Opnd> { 482 bit isBarrier = 1; 483 list<Register> Defs = [AT]; 484 } 485 486 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO> 487 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), 488 [], II_JR, FrmR>, 489 MMR6Arch<opstr>, MicroMipsR6Inst16 { 490 let hasDelaySlot = 0; 491 let isBranch = 1; 492 let isIndirectBranch = 1; 493 } 494 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>; 495 496 class JRCADDIUSP_MMR6_DESC 497 : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm", 498 [], II_JRADDIUSP, FrmR>, 499 MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 { 500 let hasDelaySlot = 0; 501 let isTerminator = 1; 502 let isBarrier = 1; 503 let isBranch = 1; 504 let isIndirectBranch = 1; 505 } 506 507 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 508 Operand ImmOpnd> : MMR6Arch<instr_asm> { 509 dag OutOperandList = (outs GPROpnd:$rd); 510 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 511 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 512 list<dag> Pattern = []; 513 } 514 515 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>; 516 517 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 518 : MMR6Arch<instr_asm> { 519 dag OutOperandList = (outs GPROpnd:$rt); 520 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm); 521 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); 522 list<dag> Pattern = []; 523 } 524 525 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>; 526 527 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>; 528 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>; 529 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 530 : MMR6Arch<instr_asm> { 531 dag OutOperandList = (outs GPROpnd:$rt); 532 dag InOperandList = (ins simm16:$imm); 533 string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); 534 list<dag> Pattern = []; 535 } 536 537 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>; 538 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>; 539 540 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 541 Operand ImmOpnd> : MMR6Arch<instr_asm> { 542 dag OutOperandList = (outs GPROpnd:$rd); 543 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); 544 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2"); 545 list<dag> Pattern = []; 546 } 547 548 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>; 549 550 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 551 Operand ImmOpnd> : MMR6Arch<instr_asm> { 552 dag OutOperandList = (outs GPROpnd:$rt); 553 dag InOperandList = (ins ImmOpnd:$imm); 554 string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); 555 list<dag> Pattern = []; 556 } 557 558 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>; 559 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>; 560 561 class LWP_MMR6_DESC : MMR6Arch<"lwp"> { 562 dag OutOperandList = (outs regpair:$rd); 563 dag InOperandList = (ins mem_simm12:$addr); 564 string AsmString = !strconcat("lwp", "\t$rd, $addr"); 565 list<dag> Pattern = []; 566 InstrItinClass Itin = NoItinerary; 567 ComplexPattern Addr = addr; 568 Format f = FrmI; 569 string BaseOpcode = "lwp"; 570 string DecoderMethod = "DecodeMemMMImm12"; 571 bit mayLoad = 1; 572 } 573 574 class SWP_MMR6_DESC : MMR6Arch<"swp"> { 575 dag OutOperandList = (outs); 576 dag InOperandList = (ins regpair:$rd, mem_simm12:$addr); 577 string AsmString = !strconcat("swp", "\t$rd, $addr"); 578 list<dag> Pattern = []; 579 InstrItinClass Itin = NoItinerary; 580 ComplexPattern Addr = addr; 581 Format f = FrmI; 582 string BaseOpcode = "swp"; 583 string DecoderMethod = "DecodeMemMMImm12"; 584 bit mayStore = 1; 585 } 586 587 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 588 : MMR6Arch<instr_asm> { 589 dag OutOperandList = (outs GPROpnd:$rd); 590 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 591 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 592 list<dag> Pattern = []; 593 } 594 595 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>; 596 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>; 597 class PAUSE_MMR6_DESC : Barrier<"pause">; 598 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst { 599 dag OutOperandList = (outs GPR32Opnd:$rt); 600 dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel); 601 string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel"); 602 list<dag> Pattern = []; 603 InstrItinClass Itinerary = II_RDHWR; 604 Format Form = FrmR; 605 } 606 607 class WAIT_MMR6_DESC : WaitMM<"wait">; 608 class SSNOP_MMR6_DESC : Barrier<"ssnop">; 609 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>; 610 611 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd, 612 SDPatternOperator OpNode=null_frag> 613 : MipsR6Inst { 614 dag OutOperandList = (outs GPROpnd:$rd); 615 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 616 string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt"); 617 list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))]; 618 string BaseOpcode = opstr; 619 Format f = FrmR; 620 let isCommutable = 0; 621 let isReMaterializable = 1; 622 623 // This instruction doesn't trap division by zero itself. We must insert 624 // teq instructions as well. 625 bit usesCustomInserter = 1; 626 } 627 class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>; 628 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>; 629 class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>; 630 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>; 631 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>; 632 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>; 633 class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>; 634 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>; 635 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, 636 or> { 637 int AddedComplexity = 1; 638 } 639 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>; 640 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, 641 immZExt16, xor>; 642 643 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO, 644 SDPatternOperator OpNode = null_frag, 645 InstrItinClass Itin = NoItinerary, 646 ComplexPattern Addr = addr> : 647 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 648 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 649 let DecoderMethod = "DecodeMem"; 650 let mayStore = 1; 651 } 652 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>; 653 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>; 654 655 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> 656 : MMR6Arch<instr_asm> { 657 dag InOperandList = (ins RO:$rs); 658 dag OutOperandList = (outs RO:$rt); 659 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 660 list<dag> Pattern = []; 661 Format f = FrmR; 662 string BaseOpcode = instr_asm; 663 bit hasSideEffects = 0; 664 } 665 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>; 666 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>; 667 668 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, 669 RegisterOperand SrcRC> { 670 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel); 671 dag OutOperandList = (outs DstRC:$rs); 672 string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); 673 list<dag> Pattern = []; 674 Format f = FrmFR; 675 string BaseOpcode = opstr; 676 } 677 class MTC1_MMR6_DESC_BASE< 678 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 679 InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag> 680 : MipsR6Inst { 681 dag InOperandList = (ins SrcRC:$rt); 682 dag OutOperandList = (outs DstRC:$fs); 683 string AsmString = !strconcat(opstr, "\t$rt, $fs"); 684 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))]; 685 Format f = FrmFR; 686 InstrItinClass Itinerary = Itin; 687 string BaseOpcode = opstr; 688 } 689 class MTC1_64_MMR6_DESC_BASE< 690 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 691 InstrItinClass Itin = NoItinerary> : MipsR6Inst { 692 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt); 693 dag OutOperandList = (outs DstRC:$fs); 694 string AsmString = !strconcat(opstr, "\t$rt, $fs"); 695 list<dag> Pattern = []; 696 Format f = FrmFR; 697 InstrItinClass Itinerary = Itin; 698 string BaseOpcode = opstr; 699 // $fs_in is part of a white lie to work around a widespread bug in the FPU 700 // implementation. See expandBuildPairF64 for details. 701 let Constraints = "$fs = $fs_in"; 702 } 703 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, 704 RegisterOperand SrcRC> { 705 dag InOperandList = (ins SrcRC:$rt); 706 dag OutOperandList = (outs DstRC:$impl); 707 string AsmString = !strconcat(opstr, "\t$rt, $impl"); 708 list<dag> Pattern = []; 709 Format f = FrmFR; 710 string BaseOpcode = opstr; 711 } 712 713 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>; 714 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd, 715 II_MTC1, bitconvert>, HARDFLOAT; 716 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>; 717 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>; 718 class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>, 719 HARDFLOAT, FGR_32; 720 class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd>, 721 HARDFLOAT, FGR_64; 722 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>; 723 724 class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, 725 RegisterOperand SrcRC> { 726 dag InOperandList = (ins SrcRC:$rs, uimm3:$sel); 727 dag OutOperandList = (outs DstRC:$rt); 728 string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); 729 list<dag> Pattern = []; 730 Format f = FrmFR; 731 string BaseOpcode = opstr; 732 } 733 class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, 734 RegisterOperand SrcRC, 735 InstrItinClass Itin = NoItinerary, 736 SDPatternOperator OpNode = null_frag> : MipsR6Inst { 737 dag InOperandList = (ins SrcRC:$fs); 738 dag OutOperandList = (outs DstRC:$rt); 739 string AsmString = !strconcat(opstr, "\t$rt, $fs"); 740 list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))]; 741 Format f = FrmFR; 742 InstrItinClass Itinerary = Itin; 743 string BaseOpcode = opstr; 744 } 745 class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, 746 RegisterOperand SrcRC> { 747 dag InOperandList = (ins SrcRC:$impl); 748 dag OutOperandList = (outs DstRC:$rt); 749 string AsmString = !strconcat(opstr, "\t$rt, $impl"); 750 list<dag> Pattern = []; 751 Format f = FrmFR; 752 string BaseOpcode = opstr; 753 } 754 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>; 755 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd, 756 II_MFC1, bitconvert>, HARDFLOAT; 757 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>; 758 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>; 759 class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, 760 II_MFHC1>, HARDFLOAT, FGR_32; 761 class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, 762 II_MFHC1>, HARDFLOAT, FGR_64; 763 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>; 764 765 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { 766 dag InOperandList = (ins mem_mm_16:$addr); 767 dag OutOperandList = (outs FGR64Opnd:$ft); 768 string AsmString = !strconcat("ldc1", "\t$ft, $addr"); 769 list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))]; 770 Format f = FrmFI; 771 InstrItinClass Itinerary = II_LDC1; 772 string BaseOpcode = "ldc1"; 773 bit mayLoad = 1; 774 let DecoderMethod = "DecodeFMemMMR2"; 775 } 776 777 class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { 778 dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr); 779 dag OutOperandList = (outs); 780 string AsmString = !strconcat("sdc1", "\t$ft, $addr"); 781 list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)]; 782 Format f = FrmFI; 783 InstrItinClass Itinerary = II_SDC1; 784 string BaseOpcode = "sdc1"; 785 bit mayStore = 1; 786 let DecoderMethod = "DecodeFMemMMR2"; 787 } 788 789 class LDC2_LWC2_MMR6_DESC_BASE<string opstr> { 790 dag OutOperandList = (outs COP2Opnd:$rt); 791 dag InOperandList = (ins mem_mm_11:$addr); 792 string AsmString = !strconcat(opstr, "\t$rt, $addr"); 793 list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))]; 794 Format f = FrmFI; 795 InstrItinClass Itinerary = NoItinerary; 796 string BaseOpcode = opstr; 797 bit mayLoad = 1; 798 string DecoderMethod = "DecodeFMemCop2MMR6"; 799 } 800 class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2">; 801 class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2">; 802 803 class SDC2_SWC2_MMR6_DESC_BASE<string opstr> { 804 dag OutOperandList = (outs); 805 dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr); 806 string AsmString = !strconcat(opstr, "\t$rt, $addr"); 807 list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)]; 808 Format f = FrmFI; 809 InstrItinClass Itinerary = NoItinerary; 810 string BaseOpcode = opstr; 811 bit mayStore = 1; 812 string DecoderMethod = "DecodeFMemCop2MMR6"; 813 } 814 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">; 815 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">; 816 817 /// Floating Point Instructions 818 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC, 819 InstrItinClass Itin, bit isComm, 820 SDPatternOperator OpNode = null_frag> : HARDFLOAT { 821 dag OutOperandList = (outs RC:$fd); 822 dag InOperandList = (ins RC:$ft, RC:$fs); 823 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 824 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]; 825 InstrItinClass Itinerary = Itin; 826 bit isCommutable = isComm; 827 } 828 class FADD_S_MMR6_DESC 829 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>; 830 class FADD_D_MMR6_DESC 831 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>; 832 class FSUB_S_MMR6_DESC 833 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>; 834 class FSUB_D_MMR6_DESC 835 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>; 836 class FMUL_S_MMR6_DESC 837 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>; 838 class FMUL_D_MMR6_DESC 839 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>; 840 class FDIV_S_MMR6_DESC 841 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>; 842 class FDIV_D_MMR6_DESC 843 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>; 844 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT; 845 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT; 846 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT; 847 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT; 848 849 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC, 850 RegisterOperand SrcRC, InstrItinClass Itin, 851 SDPatternOperator OpNode = null_frag> 852 : HARDFLOAT, NeverHasSideEffects { 853 dag OutOperandList = (outs DstRC:$ft); 854 dag InOperandList = (ins SrcRC:$fs); 855 string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); 856 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; 857 InstrItinClass Itinerary = Itin; 858 Format Form = FrmFR; 859 } 860 class FMOV_S_MMR6_DESC 861 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>; 862 class FMOV_D_MMR6_DESC 863 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>; 864 class FNEG_S_MMR6_DESC 865 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>; 866 class FNEG_D_MMR6_DESC 867 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>; 868 869 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT; 870 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT; 871 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT; 872 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT; 873 874 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT; 875 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT; 876 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT; 877 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT; 878 879 class CVT_MMR6_DESC_BASE< 880 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC, 881 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> 882 : HARDFLOAT, NeverHasSideEffects { 883 dag OutOperandList = (outs DstRC:$ft); 884 dag InOperandList = (ins SrcRC:$fs); 885 string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); 886 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; 887 InstrItinClass Itinerary = Itin; 888 Format Form = FrmFR; 889 } 890 891 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd, 892 II_CVT>; 893 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd, 894 II_CVT>; 895 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd, 896 II_CVT>; 897 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd, 898 II_CVT>; 899 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd, 900 II_CVT>; 901 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd, 902 II_CVT>; 903 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd, 904 II_CVT>, FGR_64; 905 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd, 906 II_CVT>; 907 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd, 908 II_CVT>; 909 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd, 910 II_CVT>, FGR_64; 911 912 multiclass CMP_CC_MMR6<bits<6> format, string Typestr, 913 RegisterOperand FGROpnd> { 914 def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 915 !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>, 916 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, 917 ISA_MICROMIPS32R6; 918 def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 919 !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>, 920 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, HARDFLOAT, 921 ISA_MICROMIPS32R6; 922 def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 923 !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>, 924 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, HARDFLOAT, 925 ISA_MICROMIPS32R6; 926 def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 927 !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>, 928 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, HARDFLOAT, 929 ISA_MICROMIPS32R6; 930 def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 931 !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>, 932 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, HARDFLOAT, 933 ISA_MICROMIPS32R6; 934 def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 935 !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>, 936 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, HARDFLOAT, 937 ISA_MICROMIPS32R6; 938 def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 939 !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>, 940 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, HARDFLOAT, 941 ISA_MICROMIPS32R6; 942 def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 943 !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>, 944 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, HARDFLOAT, 945 ISA_MICROMIPS32R6; 946 def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 947 !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>, 948 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, 949 ISA_MICROMIPS32R6; 950 def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 951 !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>, 952 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, 953 ISA_MICROMIPS32R6; 954 def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 955 !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>, 956 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, 957 ISA_MICROMIPS32R6; 958 def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 959 !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>, 960 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, 961 ISA_MICROMIPS32R6; 962 def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 963 !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>, 964 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, 965 ISA_MICROMIPS32R6; 966 def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 967 !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>, 968 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, 969 ISA_MICROMIPS32R6; 970 def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 971 !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>, 972 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, 973 ISA_MICROMIPS32R6; 974 def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< 975 !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>, 976 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, 977 ISA_MICROMIPS32R6; 978 } 979 980 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC, 981 RegisterOperand SrcRC, InstrItinClass Itin, 982 SDPatternOperator OpNode = null_frag> 983 : HARDFLOAT, NeverHasSideEffects { 984 dag OutOperandList = (outs DstRC:$ft); 985 dag InOperandList = (ins SrcRC:$fs); 986 string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); 987 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; 988 InstrItinClass Itinerary = Itin; 989 Format Form = FrmFR; 990 list<Predicate> EncodingPredicates = [HasStdEnc]; 991 } 992 993 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd, 994 II_ABS, fabs>; 995 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd, 996 II_ABS, fabs>; 997 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd, 998 FGR32Opnd, II_FLOOR>; 999 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd, 1000 FGR64Opnd, II_FLOOR>; 1001 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd, 1002 FGR32Opnd, II_FLOOR>; 1003 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd, 1004 AFGR64Opnd, II_FLOOR>; 1005 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd, 1006 FGR32Opnd, II_CEIL>; 1007 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd, 1008 FGR64Opnd, II_CEIL>; 1009 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd, 1010 FGR32Opnd, II_CEIL>; 1011 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd, 1012 AFGR64Opnd, II_CEIL>; 1013 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd, 1014 FGR32Opnd, II_TRUNC>; 1015 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd, 1016 FGR64Opnd, II_TRUNC>; 1017 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd, 1018 FGR32Opnd, II_TRUNC>; 1019 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, 1020 AFGR64Opnd, II_TRUNC>; 1021 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, 1022 II_SQRT_S, fsqrt>; 1023 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, 1024 II_SQRT_D, fsqrt>; 1025 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd, 1026 FGR32Opnd, II_TRUNC>; 1027 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd, 1028 AFGR64Opnd, II_TRUNC>; 1029 class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd, 1030 FGR32Opnd, II_ROUND>; 1031 class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd, 1032 II_ROUND>; 1033 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd, 1034 FGR32Opnd, II_ROUND>; 1035 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd, 1036 FGR64Opnd, II_ROUND>; 1037 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd, 1038 FGR32Opnd, II_ROUND>; 1039 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd, 1040 FGR64Opnd, II_ROUND>; 1041 1042 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>; 1043 class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> { 1044 // We must insert a SUBREG_TO_REG around $fd_in 1045 bit usesCustomInserter = 1; 1046 } 1047 1048 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; 1049 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; 1050 class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; 1051 class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; 1052 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; 1053 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; 1054 class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; 1055 class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; 1056 1057 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO> 1058 : Store<opstr, RO>, MMR6Arch<opstr> { 1059 let DecoderMethod = "DecodeMemMMImm16"; 1060 } 1061 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>; 1062 1063 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> 1064 : MMR6Arch<instr_asm>, MipsR6Inst { 1065 dag OutOperandList = (outs); 1066 dag InOperandList = (ins RO:$rt, mem_simm9:$addr); 1067 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 1068 string DecoderMethod = "DecodeStoreEvaOpMM"; 1069 bit mayStore = 1; 1070 } 1071 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>; 1072 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>; 1073 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>; 1074 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>; 1075 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> : 1076 MMR6Arch<instr_asm>, MipsR6Inst { 1077 dag OutOperandList = (outs RO:$rt); 1078 dag InOperandList = (ins mem_simm9:$addr); 1079 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 1080 string DecoderMethod = "DecodeMemMMImm9"; 1081 bit mayLoad = 1; 1082 } 1083 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>; 1084 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>; 1085 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, 1086 MMR6Arch<"addu16"> { 1087 int AddedComplexity = 1; 1088 } 1089 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, 1090 MMR6Arch<"and16"> { 1091 int AddedComplexity = 1; 1092 } 1093 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, 1094 MMR6Arch<"andi16">; 1095 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> { 1096 int AddedComplexity = 1; 1097 } 1098 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, 1099 MMR6Arch<"or16"> { 1100 int AddedComplexity = 1; 1101 } 1102 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, 1103 MMR6Arch<"sll16">; 1104 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, 1105 MMR6Arch<"srl16">; 1106 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">, 1107 MicroMipsR6Inst16; 1108 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, 1109 MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove; 1110 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">, 1111 MicroMipsR6Inst16; 1112 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">, 1113 MicroMipsR6Inst16; 1114 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, 1115 MMR6Arch<"subu16">, MicroMipsR6Inst16 { 1116 int AddedComplexity = 1; 1117 } 1118 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, 1119 MMR6Arch<"xor16"> { 1120 int AddedComplexity = 1; 1121 } 1122 1123 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst { 1124 dag OutOperandList = (outs GPR32Opnd:$rt); 1125 dag InOperandList = (ins mem:$addr); 1126 string AsmString = "lw\t$rt, $addr"; 1127 let DecoderMethod = "DecodeMemMMImm16"; 1128 let canFoldAsLoad = 1; 1129 let mayLoad = 1; 1130 list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))]; 1131 InstrItinClass Itinerary = II_LW; 1132 } 1133 1134 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{ 1135 dag OutOperandList = (outs GPR32Opnd:$rt); 1136 dag InOperandList = (ins uimm16:$imm16); 1137 string AsmString = "lui\t$rt, $imm16"; 1138 list<dag> Pattern = []; 1139 bit hasSideEffects = 0; 1140 bit isReMaterializable = 1; 1141 InstrItinClass Itinerary = II_LUI; 1142 Format Form = FrmI; 1143 } 1144 1145 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst { 1146 dag OutOperandList = (outs); 1147 dag InOperandList = (ins uimm5:$stype); 1148 string AsmString = !strconcat("sync", "\t$stype"); 1149 list<dag> Pattern = [(MipsSync immZExt5:$stype)]; 1150 InstrItinClass Itinerary = NoItinerary; 1151 bit HasSideEffects = 1; 1152 } 1153 1154 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> { 1155 let DecoderMethod = "DecodeSynciR6"; 1156 } 1157 1158 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst { 1159 dag OutOperandList = (outs GPR32Opnd:$rt); 1160 dag InOperandList = (ins GPR32Opnd:$rd); 1161 string AsmString = !strconcat("rdpgpr", "\t$rt, $rd"); 1162 } 1163 1164 class SDBBP_MMR6_DESC : MipsR6Inst { 1165 dag OutOperandList = (outs); 1166 dag InOperandList = (ins uimm20:$code_); 1167 string AsmString = !strconcat("sdbbp", "\t$code_"); 1168 list<dag> Pattern = []; 1169 } 1170 1171 class LWM16_MMR6_DESC 1172 : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr), 1173 !strconcat("lwm16", "\t$rt, $addr"), [], 1174 NoItinerary, FrmI>, 1175 MMR6Arch<"lwm16">, MicroMipsR6Inst16 { 1176 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; 1177 let mayLoad = 1; 1178 InstrItinClass Itin = NoItinerary; 1179 ComplexPattern Addr = addr; 1180 } 1181 1182 class SWM16_MMR6_DESC 1183 : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr), 1184 !strconcat("swm16", "\t$rt, $addr"), [], 1185 NoItinerary, FrmI>, 1186 MMR6Arch<"swm16">, MicroMipsR6Inst16 { 1187 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; 1188 let mayStore = 1; 1189 InstrItinClass Itin = NoItinerary; 1190 ComplexPattern Addr = addr; 1191 } 1192 1193 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO, 1194 SDPatternOperator OpNode, InstrItinClass Itin, 1195 Operand MemOpnd> 1196 : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr), 1197 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>, 1198 MMR6Arch<opstr>, MicroMipsR6Inst16 { 1199 let DecoderMethod = "DecodeMemMMImm4"; 1200 let mayStore = 1; 1201 } 1202 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd, 1203 truncstorei8, II_SB, mem_mm_4>; 1204 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd, 1205 truncstorei16, II_SH, mem_mm_4_lsl1>; 1206 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd, 1207 store, II_SW, mem_mm_4_lsl2>; 1208 1209 class SWSP_MMR6_DESC 1210 : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1211 !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>, 1212 MMR6Arch<"sw">, MicroMipsR6Inst16 { 1213 let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; 1214 let mayStore = 1; 1215 } 1216 1217 class JALRC_HB_MMR6_DESC { 1218 dag OutOperandList = (outs GPR32Opnd:$rt); 1219 dag InOperandList = (ins GPR32Opnd:$rs); 1220 string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs"); 1221 list<dag> Pattern = []; 1222 InstrItinClass Itinerary = NoItinerary; 1223 Format Form = FrmJ; 1224 bit isIndirectBranch = 1; 1225 bit hasDelaySlot = 0; 1226 } 1227 1228 class TLBINV_MMR6_DESC_BASE<string opstr> { 1229 dag OutOperandList = (outs); 1230 dag InOperandList = (ins); 1231 string AsmString = opstr; 1232 list<dag> Pattern = []; 1233 } 1234 1235 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; 1236 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; 1237 1238 class DVPEVP_MMR6_DESC_BASE<string opstr> { 1239 dag OutOperandList = (outs); 1240 dag InOperandList = (ins GPR32Opnd:$rs); 1241 string AsmString = !strconcat(opstr, "\t$rs"); 1242 list<dag> Pattern = []; 1243 } 1244 1245 class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">; 1246 class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">; 1247 1248 class BEQZC_MMR6_DESC 1249 : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>, 1250 MMR6Arch<"beqzc">; 1251 class BNEZC_MMR6_DESC 1252 : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>, 1253 MMR6Arch<"bnezc">; 1254 1255 class BRANCH_COP1_MMR6_DESC_BASE<string opstr> : 1256 InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset), 1257 !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>, 1258 HARDFLOAT, BRANCH_DESC_BASE { 1259 list<Register> Defs = [AT]; 1260 } 1261 1262 class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">; 1263 class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">; 1264 1265 class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE { 1266 dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset); 1267 dag OutOperandList = (outs); 1268 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 1269 list<Register> Defs = [AT]; 1270 } 1271 1272 class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">; 1273 class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">; 1274 1275 class EXT_MMR6_DESC { 1276 dag OutOperandList = (outs GPR32Opnd:$rt); 1277 dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size); 1278 string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size"); 1279 list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos, 1280 imm:$size))]; 1281 InstrItinClass Itinerary = II_EXT; 1282 Format Form = FrmR; 1283 string BaseOpcode = "ext"; 1284 } 1285 1286 class INS_MMR6_DESC { 1287 dag OutOperandList = (outs GPR32Opnd:$rt); 1288 dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size, 1289 GPR32Opnd:$src); 1290 string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size"); 1291 list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos, 1292 imm:$size, GPR32Opnd:$src))]; 1293 InstrItinClass Itinerary = II_INS; 1294 Format Form = FrmR; 1295 string BaseOpcode = "ins"; 1296 string Constraints = "$src = $rt"; 1297 } 1298 1299 class JALRC_MMR6_DESC { 1300 dag OutOperandList = (outs GPR32Opnd:$rt); 1301 dag InOperandList = (ins GPR32Opnd:$rs); 1302 string AsmString = !strconcat("jalrc", "\t$rt, $rs"); 1303 list<dag> Pattern = []; 1304 InstrItinClass Itinerary = II_JALRC; 1305 bit isCall = 1; 1306 bit hasDelaySlot = 0; 1307 list<Register> Defs = [RA]; 1308 } 1309 1310 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd, 1311 RegisterOperand GPROpnd> 1312 : BRANCH_DESC_BASE { 1313 dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset); 1314 dag OutOperandList = (outs); 1315 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset"); 1316 list<Register> Defs = [AT]; 1317 } 1318 1319 class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>; 1320 class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>; 1321 1322 //===----------------------------------------------------------------------===// 1323 // 1324 // Instruction Definitions 1325 // 1326 //===----------------------------------------------------------------------===// 1327 1328 let DecoderNamespace = "MicroMipsR6" in { 1329 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; 1330 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6; 1331 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6; 1332 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC, 1333 ISA_MICROMIPS32R6; 1334 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC, 1335 ISA_MICROMIPS32R6; 1336 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6; 1337 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6; 1338 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6; 1339 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6; 1340 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6; 1341 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; 1342 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; 1343 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6; 1344 def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC, 1345 ISA_MICROMIPS32R6; 1346 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC, 1347 ISA_MICROMIPS32R6; 1348 def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC, 1349 ISA_MICROMIPS32R6; 1350 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC, 1351 ISA_MICROMIPS32R6; 1352 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, 1353 ISA_MICROMIPS32R6; 1354 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC, 1355 ISA_MICROMIPS32R6; 1356 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC, 1357 ISA_MICROMIPS32R6; 1358 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6; 1359 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; 1360 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6; 1361 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6; 1362 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6; 1363 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6; 1364 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6; 1365 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6; 1366 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6; 1367 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6; 1368 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6; 1369 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC, 1370 ISA_MICROMIPS32R6; 1371 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC, 1372 ISA_MICROMIPS32R6; 1373 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6; 1374 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6; 1375 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6; 1376 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC, 1377 ISA_MICROMIPS32R6; 1378 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6; 1379 def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6; 1380 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6; 1381 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6; 1382 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6; 1383 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6; 1384 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6; 1385 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6; 1386 def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6; 1387 let DecoderNamespace = "MicroMips32r6FP64" in { 1388 def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC, 1389 ISA_MICROMIPS32R6; 1390 } 1391 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6; 1392 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6; 1393 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6; 1394 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6; 1395 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6; 1396 def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC, 1397 ISA_MICROMIPS32R6; 1398 let DecoderNamespace = "MicroMips32r6FP64" in { 1399 def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC, 1400 ISA_MICROMIPS32R6; 1401 } 1402 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6; 1403 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6; 1404 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6; 1405 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6; 1406 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6; 1407 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6; 1408 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6; 1409 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6; 1410 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6; 1411 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6; 1412 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; 1413 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6; 1414 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6; 1415 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6; 1416 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, 1417 ISA_MICROMIPS32R6; 1418 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, 1419 ISA_MICROMIPS32R6; 1420 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6; 1421 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6; 1422 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6; 1423 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; 1424 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6; 1425 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6; 1426 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6; 1427 def SWP_MMR6 : StdMMR6Rel, SWP_MMR6_ENC, SWP_MMR6_DESC, ISA_MICROMIPS32R6; 1428 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6; 1429 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC, 1430 ISA_MICROMIPS32R6; 1431 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC, 1432 ISA_MICROMIPS32R6; 1433 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6; 1434 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6; 1435 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6; 1436 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6; 1437 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6; 1438 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6; 1439 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6; 1440 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6; 1441 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6; 1442 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6; 1443 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6; 1444 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC, 1445 ISA_MICROMIPS32R6; 1446 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6; 1447 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; 1448 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; 1449 let DecoderMethod = "DecodeMemMMImm16" in { 1450 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6; 1451 } 1452 let DecoderMethod = "DecodeMemMMImm9" in { 1453 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6; 1454 } 1455 /// Floating Point Instructions 1456 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC, 1457 ISA_MICROMIPS32R6; 1458 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC, 1459 ISA_MICROMIPS32R6; 1460 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC, 1461 ISA_MICROMIPS32R6; 1462 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC, 1463 ISA_MICROMIPS32R6; 1464 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC, 1465 ISA_MICROMIPS32R6; 1466 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC, 1467 ISA_MICROMIPS32R6; 1468 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC, 1469 ISA_MICROMIPS32R6; 1470 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC, 1471 ISA_MICROMIPS32R6; 1472 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC, 1473 ISA_MICROMIPS32R6; 1474 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC, 1475 ISA_MICROMIPS32R6; 1476 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC, 1477 ISA_MICROMIPS32R6; 1478 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC, 1479 ISA_MICROMIPS32R6; 1480 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC, 1481 ISA_MICROMIPS32R6; 1482 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC, 1483 ISA_MICROMIPS32R6; 1484 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC, 1485 ISA_MICROMIPS32R6; 1486 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC, 1487 ISA_MICROMIPS32R6; 1488 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6; 1489 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6; 1490 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6; 1491 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6; 1492 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC, 1493 ISA_MICROMIPS32R6; 1494 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC, 1495 ISA_MICROMIPS32R6; 1496 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC, 1497 ISA_MICROMIPS32R6; 1498 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC, 1499 ISA_MICROMIPS32R6; 1500 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC, 1501 ISA_MICROMIPS32R6; 1502 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC, 1503 ISA_MICROMIPS32R6; 1504 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC, 1505 ISA_MICROMIPS32R6; 1506 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC, 1507 ISA_MICROMIPS32R6; 1508 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC, 1509 ISA_MICROMIPS32R6; 1510 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC, 1511 ISA_MICROMIPS32R6; 1512 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC, 1513 ISA_MICROMIPS32R6; 1514 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC, 1515 ISA_MICROMIPS32R6; 1516 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC, 1517 ISA_MICROMIPS32R6; 1518 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC, 1519 ISA_MICROMIPS32R6; 1520 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>; 1521 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>; 1522 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6; 1523 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6; 1524 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC, 1525 ISA_MICROMIPS32R6; 1526 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC, 1527 ISA_MICROMIPS32R6; 1528 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC, 1529 ISA_MICROMIPS32R6; 1530 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC, 1531 ISA_MICROMIPS32R6; 1532 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC, 1533 ISA_MICROMIPS32R6; 1534 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC, 1535 ISA_MICROMIPS32R6; 1536 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC, 1537 ISA_MICROMIPS32R6; 1538 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC, 1539 ISA_MICROMIPS32R6; 1540 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC, 1541 ISA_MICROMIPS32R6; 1542 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC, 1543 ISA_MICROMIPS32R6; 1544 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC, 1545 ISA_MICROMIPS32R6; 1546 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC, 1547 ISA_MICROMIPS32R6; 1548 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC, 1549 ISA_MICROMIPS32R6; 1550 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC, 1551 ISA_MICROMIPS32R6; 1552 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC, 1553 ISA_MICROMIPS32R6; 1554 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC, 1555 ISA_MICROMIPS32R6; 1556 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6; 1557 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6; 1558 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6; 1559 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6; 1560 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6; 1561 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6; 1562 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6; 1563 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6; 1564 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6; 1565 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC, 1566 ISA_MICROMIPS32R6; 1567 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC, 1568 ISA_MICROMIPS32R6; 1569 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC, 1570 ISA_MICROMIPS32R6; 1571 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC, 1572 ISA_MICROMIPS32R6; 1573 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC, 1574 ISA_MICROMIPS32R6; 1575 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC, 1576 ISA_MICROMIPS32R6; 1577 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC, 1578 ISA_MICROMIPS32R6; 1579 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC, 1580 ISA_MICROMIPS32R6; 1581 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC, 1582 ISA_MICROMIPS32R6; 1583 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC, 1584 ISA_MICROMIPS32R6; 1585 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC, 1586 ISA_MICROMIPS32R6; 1587 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC, 1588 ISA_MICROMIPS32R6; 1589 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, 1590 ISA_MICROMIPS32R6; 1591 def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, 1592 ISA_MICROMIPS32R6; 1593 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6; 1594 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6; 1595 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6; 1596 def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC, 1597 ISA_MICROMIPS32R6; 1598 def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6; 1599 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC, 1600 ISA_MICROMIPS32R6; 1601 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6; 1602 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC, 1603 ISA_MICROMIPS32R6; 1604 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC, 1605 ISA_MICROMIPS32R6; 1606 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC, 1607 ISA_MICROMIPS32R6; 1608 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC, 1609 ISA_MICROMIPS32R6; 1610 def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6; 1611 def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6; 1612 def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC, 1613 ISA_MICROMIPS32R6; 1614 def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC, 1615 ISA_MICROMIPS32R6; 1616 def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC, 1617 ISA_MICROMIPS32R6; 1618 def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC, 1619 ISA_MICROMIPS32R6; 1620 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC, 1621 ISA_MICROMIPS32R6; 1622 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, 1623 ISA_MICROMIPS32R6; 1624 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC, 1625 ISA_MICROMIPS32R6; 1626 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, 1627 ISA_MICROMIPS32R6; 1628 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6; 1629 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6; 1630 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC, 1631 ISA_MICROMIPS32R6; 1632 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC, 1633 ISA_MICROMIPS32R6; 1634 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC, 1635 ISA_MICROMIPS32R6; 1636 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC, 1637 ISA_MICROMIPS32R6; 1638 let DecoderNamespace = "MicroMips32r6FP64" in { 1639 def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC, 1640 ISA_MICROMIPS32R6 { 1641 let BaseOpcode = "LDC164"; 1642 } 1643 def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC, 1644 ISA_MICROMIPS32R6; 1645 } 1646 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6; 1647 def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6; 1648 def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6; 1649 def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6; 1650 } 1651 1652 def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6, 1653 MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">; 1654 def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6, 1655 MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">; 1656 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6; 1657 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6; 1658 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6; 1659 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6; 1660 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6, 1661 DecodeDisambiguates<"POP35GroupBranchMMR6">; 1662 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6, 1663 DecodeDisambiguates<"POP37GroupBranchMMR6">; 1664 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC, 1665 ISA_MICROMIPS32R6; 1666 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC, 1667 ISA_MICROMIPS32R6; 1668 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC, 1669 ISA_MICROMIPS32R6; 1670 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC, 1671 ISA_MICROMIPS32R6; 1672 1673 //===----------------------------------------------------------------------===// 1674 // 1675 // MicroMips instruction aliases 1676 // 1677 //===----------------------------------------------------------------------===// 1678 1679 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; 1680 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; 1681 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6; 1682 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), 1683 !strconcat("b", "\t$offset")> { 1684 string DecoderNamespace = "MicroMipsR6"; 1685 } 1686 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6; 1687 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6; 1688 def : MipsInstAlias<"rdhwr $rt, $rs", 1689 (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, 1690 ISA_MICROMIPS32R6; 1691 def : MipsInstAlias<"mtc0 $rt, $rs", 1692 (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, 1693 ISA_MICROMIPS32R6; 1694 def : MipsInstAlias<"mthc0 $rt, $rs", 1695 (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, 1696 ISA_MICROMIPS32R6; 1697 def : MipsInstAlias<"mfc0 $rt, $rs", 1698 (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, 1699 ISA_MICROMIPS32R6; 1700 def : MipsInstAlias<"mfhc0 $rt, $rs", 1701 (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, 1702 ISA_MICROMIPS32R6; 1703 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>, 1704 ISA_MICROMIPS32R6; 1705 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; 1706 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; 1707 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>, 1708 ISA_MICROMIPS32R6; 1709 def : MipsInstAlias<"and $rs, $rt, $imm", 1710 (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, 1711 ISA_MICROMIPS32R6; 1712 def : MipsInstAlias<"and $rs, $imm", 1713 (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, 1714 ISA_MICROMIPS32R6; 1715 def : MipsInstAlias<"or $rs, $rt, $imm", 1716 (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, 1717 ISA_MICROMIPS32R6; 1718 def : MipsInstAlias<"or $rs, $imm", 1719 (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, 1720 ISA_MICROMIPS32R6; 1721 def : MipsInstAlias<"xor $rs, $rt, $imm", 1722 (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, 1723 ISA_MICROMIPS32R6; 1724 def : MipsInstAlias<"xor $rs, $imm", 1725 (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, 1726 ISA_MICROMIPS32R6; 1727 def : MipsInstAlias<"not $rt, $rs", 1728 (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, 1729 ISA_MICROMIPS32R6; 1730 1731 //===----------------------------------------------------------------------===// 1732 // 1733 // MicroMips arbitrary patterns that map to one or more instructions 1734 // 1735 //===----------------------------------------------------------------------===// 1736 1737 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), 1738 (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6; 1739 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1740 (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6; 1741 1742 def : MipsPat<(select i32:$cond, i32:$t, i32:$f), 1743 (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond), 1744 (SELEQZ_MMR6 i32:$f, i32:$cond))>, 1745 ISA_MICROMIPS32R6; 1746 def : MipsPat<(select i32:$cond, i32:$t, immz), 1747 (SELNEZ_MMR6 i32:$t, i32:$cond)>, 1748 ISA_MICROMIPS32R6; 1749 def : MipsPat<(select i32:$cond, immz, i32:$f), 1750 (SELEQZ_MMR6 i32:$f, i32:$cond)>, 1751 ISA_MICROMIPS32R6; 1752 1753 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6, 1754 SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6; 1755 1756 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; 1757 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; 1758 1759 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), 1760 (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, 1761 ISA_MICROMIPS32R6; 1762 def : MipsPat<(and GPR32:$src, immZExt16:$imm), 1763 (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6; 1764 def : MipsPat<(i32 immZExt16:$imm), 1765 (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6; 1766 def : MipsPat<(not GPRMM16:$in), 1767 (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6; 1768 def : MipsPat<(not GPR32:$in), 1769 (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6; 1770 // Patterns for load with a reg+imm operand. 1771 let AddedComplexity = 41 in { 1772 def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6; 1773 def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6; 1774 } 1775
