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  /external/llvm/test/CodeGen/MIR/X86/
unknown-subregister-index-op.mir 23 ; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8'
24 %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
unknown-subregister-index.mir 24 ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
25 %1 = COPY %0:bit8
  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530.h 36 #define PBIASLITEVMODE1 BIT8
Omap3530MMCHS.h 44 #define WPP BIT8
89 #define SDBP_MASK BIT8
91 #define SDBP_ON BIT8
182 #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
Omap3530Usb.h 27 #define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
Omap3530Dma.h 89 #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
117 #define DMA4_CSR_TRANS_ERR BIT8
Omap3530I2c.h 44 #define XSA BIT8
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530.h 36 #define PBIASLITEVMODE1 BIT8
Omap3530MMCHS.h 44 #define WPP BIT8
89 #define SDBP_MASK BIT8
91 #define SDBP_ON BIT8
182 #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
Omap3530Usb.h 27 #define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
Omap3530Dma.h 89 #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
117 #define DMA4_CSR_TRANS_ERR BIT8
Omap3530I2c.h 44 #define XSA BIT8
  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h 31 #define CTRL4_PICO_OGDISABLE BIT8
43 #define CTRL5_PICOPHY_VDATDETENB BIT8
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h 25 #undef BIT8
61 #define BIT8 0x00000100U
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h 78 #define MCI_CLOCK_ENABLE BIT8
91 #define MCI_STATUS_CMD_DATAEND BIT8
144 #define MCI_CPSM_LONG_INTERRUPT BIT8
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h 50 #define ISP1761_DC_INTERRUPT_EP0SETUP BIT8
62 #define ISP1761_MODE_DATA_BUS_WIDTH BIT8
  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsUsb.h 71 #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
94 #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
PchRegsLpss.h 66 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
120 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
151 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
205 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
238 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
292 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
325 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
379 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
417 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
471 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
    [all...]
PchRegsPcu.h 77 #define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable
94 #define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error
202 #define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable
242 #define B_PCH_LPC_CGC_SBTCG BIT8 // IOSF-SB Trunk Clock Gating (Request) Disable
297 #define B_PCH_ILB_ULKMC_TRAPBY60R BIT8 // SMI Caused by Port 60 Read
315 #define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable
363 #define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) // INTC Mask
365 #define V_PCH_ILB_DXXIR_ICR_PIRQB BIT8 // INTC Mapping to IRQ B
367 #define V_PCH_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) // INTC Mapping to IRQ D
369 #define V_PCH_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) // INTC Mapping to IRQ F
    [all...]
PchRegsSata.h 69 #define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable
86 #define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected
161 #define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
177 #define B_PCH_SATA_PORT0_DISABLED BIT8
193 #define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
  /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
PciPowerManagement.c 86 PowerManagementCSR &= ~(BIT8 | BIT1 | BIT0);
  /device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h 52 #define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h 82 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)
96 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt
108 #define INSTS_TSFF BIT8 // Tx Status FIFO full
142 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable
149 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
175 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability
203 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit
252 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
PciPowerManagement.c 73 PowerManagementCSR &= ~(BIT8 | BIT1 | BIT0);
  /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h 72 BIT10 | BIT9 | BIT8 | BIT7)

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