1 /** @file 2 * 3 * Copyright (c) 2014-2015, Linaro Limited. All rights reserved. 4 * Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __HI6220_H__ 17 #define __HI6220_H__ 18 19 /*********************************************************************************** 20 // Platform Memory Map 21 ************************************************************************************/ 22 23 // SOC peripherals (UART, I2C, I2S, USB, etc) 24 #define HI6220_PERIPH_BASE 0xF4000000 25 #define HI6220_PERIPH_SZ 0x05800000 26 27 #define PERI_CTRL_BASE 0xF7030000 28 #define SC_PERIPH_CTRL4 0x00C 29 #define CTRL4_FPGA_EXT_PHY_SEL BIT3 30 #define CTRL4_PICO_SIDDQ BIT6 31 #define CTRL4_PICO_OGDISABLE BIT8 32 #define CTRL4_PICO_VBUSVLDEXT BIT10 33 #define CTRL4_PICO_VBUSVLDEXTSEL BIT11 34 #define CTRL4_OTG_PHY_SEL BIT21 35 36 #define SC_PERIPH_CTRL5 0x010 37 38 #define CTRL5_USBOTG_RES_SEL BIT3 39 #define CTRL5_PICOPHY_ACAENB BIT4 40 #define CTRL5_PICOPHY_BC_MODE BIT5 41 #define CTRL5_PICOPHY_CHRGSEL BIT6 42 #define CTRL5_PICOPHY_VDATSRCEND BIT7 43 #define CTRL5_PICOPHY_VDATDETENB BIT8 44 #define CTRL5_PICOPHY_DCDENB BIT9 45 #define CTRL5_PICOPHY_IDDIG BIT10 46 47 #define SC_PERIPH_CTRL8 0x018 48 #define SC_PERIPH_CLKEN0 0x200 49 #define SC_PERIPH_CLKDIS0 0x204 50 #define SC_PERIPH_CLKSTAT0 0x208 51 52 #define SC_PERIPH_RSTEN0 0x300 53 #define SC_PERIPH_RSTDIS0 0x304 54 #define SC_PERIPH_RSTSTAT0 0x308 55 56 #define RST0_USBOTG_BUS BIT4 57 #define RST0_POR_PICOPHY BIT5 58 #define RST0_USBOTG BIT6 59 #define RST0_USBOTG_32K BIT7 60 61 #define EYE_PATTERN_PARA 0x7053348c 62 63 #define MDDRC_AXI_BASE 0xF7120000 64 #define AXI_REGION_MAP_OFFSET(x) ( 0x100 + ( x ) * 0x10 ) 65 66 #define AO_CTRL_BASE 0xF7800000 67 #define SC_PW_MTCMOS_EN0 0x830 68 #define SC_PW_MTCMOS_DIS0 0x834 69 #define SC_PW_MTCMOS_STAT0 0x838 70 #define SC_PW_MTCMOS_ACK_STAT0 0x83c 71 #define PW_EN0_G3D (1 << 1) 72 73 #define PMUSSI_BASE 0xF8000000 74 75 #endif /* __HI6220_H__ */ 76
