1 %default {"extract": "asr w1, w3, #8", "preinstr":"", "result":"w0", "chkzero":"0"} 2 /* 3 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 4 * that specifies an instruction that performs "result = w0 op w1". 5 * This could be an ARM instruction or a function call. (If the result 6 * comes back in a register other than w0, you can override "result".) 7 * 8 * You can override "extract" if the extraction of the literal value 9 * from w3 to w1 is not the default "asr w1, w3, #8". The extraction 10 * can be omitted completely if the shift is embedded in "instr". 11 * 12 * If "chkzero" is set to 1, we perform a divide-by-zero check on 13 * vCC (w1). Useful for integer division and modulus. 14 * 15 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 16 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 17 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 18 */ 19 /* binop/lit8 vAA, vBB, #+CC */ 20 FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) 21 lsr w9, wINST, #8 // w9<- AA 22 and w2, w3, #255 // w2<- BB 23 GET_VREG w0, w2 // w0<- vBB 24 $extract // optional; typically w1<- ssssssCC (sign extended) 25 .if $chkzero 26 cbz w1, common_errDivideByZero 27 .endif 28 FETCH_ADVANCE_INST 2 // advance rPC, load rINST 29 $preinstr // optional op; may set condition codes 30 $instr // $result<- op, w0-w3 changed 31 GET_INST_OPCODE ip // extract opcode from rINST 32 SET_VREG $result, w9 // vAA<- $result 33 GOTO_OPCODE ip // jump to next instruction 34 /* 10-12 instructions */ 35
