1 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 2 srl a4, rINST, 8 # a4 <- AA 3 lh a0, 2(rPC) # a0 <- bbbb (low) 4 lh a1, 4(rPC) # a1 <- BBBB (low middle) 5 lh a2, 6(rPC) # a2 <- hhhh (high middle) 6 lh a3, 8(rPC) # a3 <- HHHH (high) 7 FETCH_ADVANCE_INST 5 # advance rPC, load rINST 8 ins a0, a1, 16, 16 # a0 = BBBBbbbb 9 ins a2, a3, 16, 16 # a2 = HHHHhhhh 10 dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb 11 GET_INST_OPCODE v0 # extract opcode from rINST 12 SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb 13 GOTO_OPCODE v0 # jump to next instruction 14
