1 %default {"wide":"0"} 2 /* 3 * Generic 32-bit "shift/2addr" operation. 4 */ 5 /* shift/2addr vA, vB */ 6 movl rINST, %ecx # ecx <- BA 7 sarl $$4, %ecx # ecx <- B 8 GET_VREG %ecx, %rcx # ecx <- vBB 9 andb $$0xf, rINSTbl # rINST <- A 10 .if $wide 11 GET_WIDE_VREG %rax, rINSTq # rax <- vAA 12 $instr # ex: sarl %cl, %eax 13 SET_WIDE_VREG %rax, rINSTq 14 .else 15 GET_VREG %eax, rINSTq # eax <- vAA 16 $instr # ex: sarl %cl, %eax 17 SET_VREG %eax, rINSTq 18 .endif 19 ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 20
