1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_EXYNOS_DRM_H_ 20 #define _UAPI_EXYNOS_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #endif 25 struct drm_exynos_gem_create { 26 __u64 size; 27 __u32 flags; 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 __u32 handle; 30 }; 31 struct drm_exynos_gem_map { 32 __u32 handle; 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 __u32 reserved; 35 __u64 offset; 36 }; 37 struct drm_exynos_gem_info { 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 __u32 handle; 40 __u32 flags; 41 __u64 size; 42 }; 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 struct drm_exynos_vidi_connection { 45 __u32 connection; 46 __u32 extensions; 47 __u64 edid; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 }; 50 enum e_drm_exynos_gem_mem_type { 51 EXYNOS_BO_CONTIG = 0 << 0, 52 EXYNOS_BO_NONCONTIG = 1 << 0, 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 EXYNOS_BO_NONCACHABLE = 0 << 1, 55 EXYNOS_BO_CACHABLE = 1 << 1, 56 EXYNOS_BO_WC = 1 << 2, 57 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 }; 60 struct drm_exynos_g2d_get_ver { 61 __u32 major; 62 __u32 minor; 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 struct drm_exynos_g2d_cmd { 66 __u32 offset; 67 __u32 data; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 }; 70 enum drm_exynos_g2d_buf_type { 71 G2D_BUF_USERPTR = 1 << 31, 72 }; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 enum drm_exynos_g2d_event_type { 75 G2D_EVENT_NOT, 76 G2D_EVENT_NONSTOP, 77 G2D_EVENT_STOP, 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 }; 80 struct drm_exynos_g2d_userptr { 81 unsigned long userptr; 82 unsigned long size; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 }; 85 struct drm_exynos_g2d_set_cmdlist { 86 __u64 cmd; 87 __u64 cmd_buf; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __u32 cmd_nr; 90 __u32 cmd_buf_nr; 91 __u64 event_type; 92 __u64 user_data; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 }; 95 struct drm_exynos_g2d_exec { 96 __u64 async; 97 }; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 enum drm_exynos_ops_id { 100 EXYNOS_DRM_OPS_SRC, 101 EXYNOS_DRM_OPS_DST, 102 EXYNOS_DRM_OPS_MAX, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 }; 105 struct drm_exynos_sz { 106 __u32 hsize; 107 __u32 vsize; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 }; 110 struct drm_exynos_pos { 111 __u32 x; 112 __u32 y; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 w; 115 __u32 h; 116 }; 117 enum drm_exynos_flip { 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 EXYNOS_DRM_FLIP_NONE = (0 << 0), 120 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 121 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 122 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL, 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 }; 125 enum drm_exynos_degree { 126 EXYNOS_DRM_DEGREE_0, 127 EXYNOS_DRM_DEGREE_90, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 EXYNOS_DRM_DEGREE_180, 130 EXYNOS_DRM_DEGREE_270, 131 }; 132 enum drm_exynos_planer { 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 EXYNOS_DRM_PLANAR_Y, 135 EXYNOS_DRM_PLANAR_CB, 136 EXYNOS_DRM_PLANAR_CR, 137 EXYNOS_DRM_PLANAR_MAX, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 }; 140 struct drm_exynos_ipp_prop_list { 141 __u32 version; 142 __u32 ipp_id; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 __u32 count; 145 __u32 writeback; 146 __u32 flip; 147 __u32 degree; 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 __u32 csc; 150 __u32 crop; 151 __u32 scale; 152 __u32 refresh_min; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 __u32 refresh_max; 155 __u32 reserved; 156 struct drm_exynos_sz crop_min; 157 struct drm_exynos_sz crop_max; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 struct drm_exynos_sz scale_min; 160 struct drm_exynos_sz scale_max; 161 }; 162 struct drm_exynos_ipp_config { 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 __u32 ops_id; 165 __u32 flip; 166 __u32 degree; 167 __u32 fmt; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 struct drm_exynos_sz sz; 170 struct drm_exynos_pos pos; 171 }; 172 enum drm_exynos_ipp_cmd { 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 IPP_CMD_NONE, 175 IPP_CMD_M2M, 176 IPP_CMD_WB, 177 IPP_CMD_OUTPUT, 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 IPP_CMD_MAX, 180 }; 181 struct drm_exynos_ipp_property { 182 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 __u32 cmd; 185 __u32 ipp_id; 186 __u32 prop_id; 187 __u32 refresh_rate; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 }; 190 enum drm_exynos_ipp_buf_type { 191 IPP_BUF_ENQUEUE, 192 IPP_BUF_DEQUEUE, 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 }; 195 struct drm_exynos_ipp_queue_buf { 196 __u32 ops_id; 197 __u32 buf_type; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __u32 prop_id; 200 __u32 buf_id; 201 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 202 __u32 reserved; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 __u64 user_data; 205 }; 206 enum drm_exynos_ipp_ctrl { 207 IPP_CTRL_PLAY, 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 IPP_CTRL_STOP, 210 IPP_CTRL_PAUSE, 211 IPP_CTRL_RESUME, 212 IPP_CTRL_MAX, 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 }; 215 struct drm_exynos_ipp_cmd_ctrl { 216 __u32 prop_id; 217 __u32 ctrl; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 }; 220 #define DRM_EXYNOS_GEM_CREATE 0x00 221 #define DRM_EXYNOS_GEM_MAP 0x01 222 #define DRM_EXYNOS_GEM_GET 0x04 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 225 #define DRM_EXYNOS_G2D_GET_VER 0x20 226 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 227 #define DRM_EXYNOS_G2D_EXEC 0x22 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 230 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 231 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 232 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 235 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) 236 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 237 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 240 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 241 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 242 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 245 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 246 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 247 #define DRM_EXYNOS_G2D_EVENT 0x80000000 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define DRM_EXYNOS_IPP_EVENT 0x80000001 250 struct drm_exynos_g2d_event { 251 struct drm_event base; 252 __u64 user_data; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 __u32 tv_sec; 255 __u32 tv_usec; 256 __u32 cmdlist_no; 257 __u32 reserved; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 }; 260 struct drm_exynos_ipp_event { 261 struct drm_event base; 262 __u64 user_data; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 __u32 tv_sec; 265 __u32 tv_usec; 266 __u32 prop_id; 267 __u32 reserved; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 270 }; 271 #ifdef __cplusplus 272 #endif 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #endif 275
