1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #endif 25 #define DRM_AMDGPU_GEM_CREATE 0x00 26 #define DRM_AMDGPU_GEM_MMAP 0x01 27 #define DRM_AMDGPU_CTX 0x02 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define DRM_AMDGPU_BO_LIST 0x03 30 #define DRM_AMDGPU_CS 0x04 31 #define DRM_AMDGPU_INFO 0x05 32 #define DRM_AMDGPU_GEM_METADATA 0x06 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 35 #define DRM_AMDGPU_GEM_VA 0x08 36 #define DRM_AMDGPU_WAIT_CS 0x09 37 #define DRM_AMDGPU_GEM_OP 0x10 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define DRM_AMDGPU_GEM_USERPTR 0x11 40 #define DRM_AMDGPU_WAIT_FENCES 0x12 41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 45 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 46 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 47 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 50 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 51 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 52 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 55 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 56 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 57 #define AMDGPU_GEM_DOMAIN_CPU 0x1 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define AMDGPU_GEM_DOMAIN_GTT 0x2 60 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 61 #define AMDGPU_GEM_DOMAIN_GDS 0x8 62 #define AMDGPU_GEM_DOMAIN_GWS 0x10 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define AMDGPU_GEM_DOMAIN_OA 0x20 65 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 66 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 67 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 70 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 71 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 72 struct drm_amdgpu_gem_create_in { 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 __u64 bo_size; 75 __u64 alignment; 76 __u64 domains; 77 __u64 domain_flags; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 }; 80 struct drm_amdgpu_gem_create_out { 81 __u32 handle; 82 __u32 _pad; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 }; 85 union drm_amdgpu_gem_create { 86 struct drm_amdgpu_gem_create_in in; 87 struct drm_amdgpu_gem_create_out out; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 }; 90 #define AMDGPU_BO_LIST_OP_CREATE 0 91 #define AMDGPU_BO_LIST_OP_DESTROY 1 92 #define AMDGPU_BO_LIST_OP_UPDATE 2 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 struct drm_amdgpu_bo_list_in { 95 __u32 operation; 96 __u32 list_handle; 97 __u32 bo_number; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u32 bo_info_size; 100 __u64 bo_info_ptr; 101 }; 102 struct drm_amdgpu_bo_list_entry { 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u32 bo_handle; 105 __u32 bo_priority; 106 }; 107 struct drm_amdgpu_bo_list_out { 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 __u32 list_handle; 110 __u32 _pad; 111 }; 112 union drm_amdgpu_bo_list { 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 struct drm_amdgpu_bo_list_in in; 115 struct drm_amdgpu_bo_list_out out; 116 }; 117 #define AMDGPU_CTX_OP_ALLOC_CTX 1 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define AMDGPU_CTX_OP_FREE_CTX 2 120 #define AMDGPU_CTX_OP_QUERY_STATE 3 121 #define AMDGPU_CTX_NO_RESET 0 122 #define AMDGPU_CTX_GUILTY_RESET 1 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define AMDGPU_CTX_INNOCENT_RESET 2 125 #define AMDGPU_CTX_UNKNOWN_RESET 3 126 struct drm_amdgpu_ctx_in { 127 __u32 op; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 __u32 flags; 130 __u32 ctx_id; 131 __u32 _pad; 132 }; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 union drm_amdgpu_ctx_out { 135 struct { 136 __u32 ctx_id; 137 __u32 _pad; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 } alloc; 140 struct { 141 __u64 flags; 142 __u32 hangs; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 __u32 reset_status; 145 } state; 146 }; 147 union drm_amdgpu_ctx { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 struct drm_amdgpu_ctx_in in; 150 union drm_amdgpu_ctx_out out; 151 }; 152 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 155 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 156 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 157 struct drm_amdgpu_gem_userptr { 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 __u64 addr; 160 __u64 size; 161 __u32 flags; 162 __u32 handle; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 }; 165 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 166 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 167 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 170 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 171 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 172 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 175 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 176 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 177 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 180 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 181 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 182 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 185 #define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 186 #define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 187 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 190 struct drm_amdgpu_gem_metadata { 191 __u32 handle; 192 __u32 op; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 struct { 195 __u64 flags; 196 __u64 tiling_info; 197 __u32 data_size_bytes; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 __u32 data[64]; 200 } data; 201 }; 202 struct drm_amdgpu_gem_mmap_in { 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 __u32 handle; 205 __u32 _pad; 206 }; 207 struct drm_amdgpu_gem_mmap_out { 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __u64 addr_ptr; 210 }; 211 union drm_amdgpu_gem_mmap { 212 struct drm_amdgpu_gem_mmap_in in; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 struct drm_amdgpu_gem_mmap_out out; 215 }; 216 struct drm_amdgpu_gem_wait_idle_in { 217 __u32 handle; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u32 flags; 220 __u64 timeout; 221 }; 222 struct drm_amdgpu_gem_wait_idle_out { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 __u32 status; 225 __u32 domain; 226 }; 227 union drm_amdgpu_gem_wait_idle { 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 struct drm_amdgpu_gem_wait_idle_in in; 230 struct drm_amdgpu_gem_wait_idle_out out; 231 }; 232 struct drm_amdgpu_wait_cs_in { 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __u64 handle; 235 __u64 timeout; 236 __u32 ip_type; 237 __u32 ip_instance; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 __u32 ring; 240 __u32 ctx_id; 241 }; 242 struct drm_amdgpu_wait_cs_out { 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 __u64 status; 245 }; 246 union drm_amdgpu_wait_cs { 247 struct drm_amdgpu_wait_cs_in in; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 struct drm_amdgpu_wait_cs_out out; 250 }; 251 struct drm_amdgpu_fence { 252 __u32 ctx_id; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 __u32 ip_type; 255 __u32 ip_instance; 256 __u32 ring; 257 __u64 seq_no; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 }; 260 struct drm_amdgpu_wait_fences_in { 261 __u64 fences; 262 __u32 fence_count; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 __u32 wait_all; 265 __u64 timeout_ns; 266 }; 267 struct drm_amdgpu_wait_fences_out { 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 __u32 status; 270 __u32 first_signaled; 271 }; 272 union drm_amdgpu_wait_fences { 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 struct drm_amdgpu_wait_fences_in in; 275 struct drm_amdgpu_wait_fences_out out; 276 }; 277 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 280 struct drm_amdgpu_gem_op { 281 __u32 handle; 282 __u32 op; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 __u64 value; 285 }; 286 #define AMDGPU_VA_OP_MAP 1 287 #define AMDGPU_VA_OP_UNMAP 2 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 290 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 291 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 292 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 struct drm_amdgpu_gem_va { 295 __u32 handle; 296 __u32 _pad; 297 __u32 operation; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 __u32 flags; 300 __u64 va_address; 301 __u64 offset_in_bo; 302 __u64 map_size; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 }; 305 #define AMDGPU_HW_IP_GFX 0 306 #define AMDGPU_HW_IP_COMPUTE 1 307 #define AMDGPU_HW_IP_DMA 2 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define AMDGPU_HW_IP_UVD 3 310 #define AMDGPU_HW_IP_VCE 4 311 #define AMDGPU_HW_IP_NUM 5 312 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define AMDGPU_CHUNK_ID_IB 0x01 315 #define AMDGPU_CHUNK_ID_FENCE 0x02 316 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 317 struct drm_amdgpu_cs_chunk { 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 __u32 chunk_id; 320 __u32 length_dw; 321 __u64 chunk_data; 322 }; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 struct drm_amdgpu_cs_in { 325 __u32 ctx_id; 326 __u32 bo_list_handle; 327 __u32 num_chunks; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 __u32 _pad; 330 __u64 chunks; 331 }; 332 struct drm_amdgpu_cs_out { 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 __u64 handle; 335 }; 336 union drm_amdgpu_cs { 337 struct drm_amdgpu_cs_in in; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 struct drm_amdgpu_cs_out out; 340 }; 341 #define AMDGPU_IB_FLAG_CE (1 << 0) 342 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 struct drm_amdgpu_cs_chunk_ib { 345 __u32 _pad; 346 __u32 flags; 347 __u64 va_start; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 __u32 ib_bytes; 350 __u32 ip_type; 351 __u32 ip_instance; 352 __u32 ring; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 }; 355 struct drm_amdgpu_cs_chunk_dep { 356 __u32 ip_type; 357 __u32 ip_instance; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 __u32 ring; 360 __u32 ctx_id; 361 __u64 handle; 362 }; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 struct drm_amdgpu_cs_chunk_fence { 365 __u32 handle; 366 __u32 offset; 367 }; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 struct drm_amdgpu_cs_chunk_data { 370 union { 371 struct drm_amdgpu_cs_chunk_ib ib_data; 372 struct drm_amdgpu_cs_chunk_fence fence_data; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 }; 375 }; 376 #define AMDGPU_IDS_FLAGS_FUSION 0x1 377 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define AMDGPU_INFO_ACCEL_WORKING 0x00 380 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 381 #define AMDGPU_INFO_HW_IP_INFO 0x02 382 #define AMDGPU_INFO_HW_IP_COUNT 0x03 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define AMDGPU_INFO_TIMESTAMP 0x05 385 #define AMDGPU_INFO_FW_VERSION 0x0e 386 #define AMDGPU_INFO_FW_VCE 0x1 387 #define AMDGPU_INFO_FW_UVD 0x2 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define AMDGPU_INFO_FW_GMC 0x03 390 #define AMDGPU_INFO_FW_GFX_ME 0x04 391 #define AMDGPU_INFO_FW_GFX_PFP 0x05 392 #define AMDGPU_INFO_FW_GFX_CE 0x06 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define AMDGPU_INFO_FW_GFX_RLC 0x07 395 #define AMDGPU_INFO_FW_GFX_MEC 0x08 396 #define AMDGPU_INFO_FW_SMC 0x0a 397 #define AMDGPU_INFO_FW_SDMA 0x0b 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 400 #define AMDGPU_INFO_VRAM_USAGE 0x10 401 #define AMDGPU_INFO_GTT_USAGE 0x11 402 #define AMDGPU_INFO_GDS_CONFIG 0x13 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define AMDGPU_INFO_VRAM_GTT 0x14 405 #define AMDGPU_INFO_READ_MMR_REG 0x15 406 #define AMDGPU_INFO_DEV_INFO 0x16 407 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 410 #define AMDGPU_INFO_MEMORY 0x19 411 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 412 #define AMDGPU_INFO_VBIOS 0x1B 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define AMDGPU_INFO_VBIOS_SIZE 0x1 415 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 416 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 417 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 420 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 421 struct drm_amdgpu_query_fw { 422 __u32 fw_type; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 __u32 ip_instance; 425 __u32 index; 426 __u32 _pad; 427 }; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 struct drm_amdgpu_info { 430 __u64 return_pointer; 431 __u32 return_size; 432 __u32 query; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 union { 435 struct { 436 __u32 id; 437 __u32 _pad; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 } mode_crtc; 440 struct { 441 __u32 type; 442 __u32 ip_instance; 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 } query_hw_ip; 445 struct { 446 __u32 dword_offset; 447 __u32 count; 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 __u32 instance; 450 __u32 flags; 451 } read_mmr_reg; 452 struct drm_amdgpu_query_fw query_fw; 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 struct { 455 __u32 type; 456 __u32 offset; 457 } vbios_info; 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 }; 460 }; 461 struct drm_amdgpu_info_gds { 462 __u32 gds_gfx_partition_size; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 __u32 compute_partition_size; 465 __u32 gds_total_size; 466 __u32 gws_per_gfx_partition; 467 __u32 gws_per_compute_partition; 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 __u32 oa_per_gfx_partition; 470 __u32 oa_per_compute_partition; 471 __u32 _pad; 472 }; 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 struct drm_amdgpu_info_vram_gtt { 475 __u64 vram_size; 476 __u64 vram_cpu_accessible_size; 477 __u64 gtt_size; 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 }; 480 struct drm_amdgpu_heap_info { 481 __u64 total_heap_size; 482 __u64 usable_heap_size; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 __u64 heap_usage; 485 __u64 max_allocation; 486 }; 487 struct drm_amdgpu_memory_info { 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 struct drm_amdgpu_heap_info vram; 490 struct drm_amdgpu_heap_info cpu_accessible_vram; 491 struct drm_amdgpu_heap_info gtt; 492 }; 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 struct drm_amdgpu_info_firmware { 495 __u32 ver; 496 __u32 feature; 497 }; 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 500 #define AMDGPU_VRAM_TYPE_GDDR1 1 501 #define AMDGPU_VRAM_TYPE_DDR2 2 502 #define AMDGPU_VRAM_TYPE_GDDR3 3 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define AMDGPU_VRAM_TYPE_GDDR4 4 505 #define AMDGPU_VRAM_TYPE_GDDR5 5 506 #define AMDGPU_VRAM_TYPE_HBM 6 507 #define AMDGPU_VRAM_TYPE_DDR3 7 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 struct drm_amdgpu_info_device { 510 __u32 device_id; 511 __u32 chip_rev; 512 __u32 external_rev; 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 __u32 pci_rev; 515 __u32 family; 516 __u32 num_shader_engines; 517 __u32 num_shader_arrays_per_engine; 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 __u32 gpu_counter_freq; 520 __u64 max_engine_clock; 521 __u64 max_memory_clock; 522 __u32 cu_active_number; 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 __u32 cu_ao_mask; 525 __u32 cu_bitmap[4][4]; 526 __u32 enabled_rb_pipes_mask; 527 __u32 num_rb_pipes; 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 __u32 num_hw_gfx_contexts; 530 __u32 _pad; 531 __u64 ids_flags; 532 __u64 virtual_address_offset; 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 __u64 virtual_address_max; 535 __u32 virtual_address_alignment; 536 __u32 pte_fragment_size; 537 __u32 gart_page_size; 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 __u32 ce_ram_size; 540 __u32 vram_type; 541 __u32 vram_bit_width; 542 __u32 vce_harvest_config; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 }; 545 struct drm_amdgpu_info_hw_ip { 546 __u32 hw_ip_version_major; 547 __u32 hw_ip_version_minor; 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 __u64 capabilities_flags; 550 __u32 ib_start_alignment; 551 __u32 ib_size_alignment; 552 __u32 available_rings; 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 __u32 _pad; 555 }; 556 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 557 struct drm_amdgpu_info_vce_clock_table_entry { 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 __u32 sclk; 560 __u32 mclk; 561 __u32 eclk; 562 __u32 pad; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 }; 565 struct drm_amdgpu_info_vce_clock_table { 566 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 567 __u32 num_valid_entries; 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 __u32 pad; 570 }; 571 #define AMDGPU_FAMILY_UNKNOWN 0 572 #define AMDGPU_FAMILY_SI 110 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 #define AMDGPU_FAMILY_CI 120 575 #define AMDGPU_FAMILY_KV 125 576 #define AMDGPU_FAMILY_VI 130 577 #define AMDGPU_FAMILY_CZ 135 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #ifdef __cplusplus 580 #endif 581 #endif 582
