1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_LINUX_PERF_EVENT_H 20 #define _UAPI_LINUX_PERF_EVENT_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <asm/byteorder.h> 25 enum perf_type_id { 26 PERF_TYPE_HARDWARE = 0, 27 PERF_TYPE_SOFTWARE = 1, 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 PERF_TYPE_TRACEPOINT = 2, 30 PERF_TYPE_HW_CACHE = 3, 31 PERF_TYPE_RAW = 4, 32 PERF_TYPE_BREAKPOINT = 5, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 PERF_TYPE_MAX, 35 }; 36 enum perf_hw_id { 37 PERF_COUNT_HW_CPU_CYCLES = 0, 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 PERF_COUNT_HW_INSTRUCTIONS = 1, 40 PERF_COUNT_HW_CACHE_REFERENCES = 2, 41 PERF_COUNT_HW_CACHE_MISSES = 3, 42 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 PERF_COUNT_HW_BRANCH_MISSES = 5, 45 PERF_COUNT_HW_BUS_CYCLES = 6, 46 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 47 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 50 PERF_COUNT_HW_MAX, 51 }; 52 enum perf_hw_cache_id { 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 PERF_COUNT_HW_CACHE_L1D = 0, 55 PERF_COUNT_HW_CACHE_L1I = 1, 56 PERF_COUNT_HW_CACHE_LL = 2, 57 PERF_COUNT_HW_CACHE_DTLB = 3, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 PERF_COUNT_HW_CACHE_ITLB = 4, 60 PERF_COUNT_HW_CACHE_BPU = 5, 61 PERF_COUNT_HW_CACHE_NODE = 6, 62 PERF_COUNT_HW_CACHE_MAX, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 enum perf_hw_cache_op_id { 66 PERF_COUNT_HW_CACHE_OP_READ = 0, 67 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 70 PERF_COUNT_HW_CACHE_OP_MAX, 71 }; 72 enum perf_hw_cache_op_result_id { 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 75 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 76 PERF_COUNT_HW_CACHE_RESULT_MAX, 77 }; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 enum perf_sw_ids { 80 PERF_COUNT_SW_CPU_CLOCK = 0, 81 PERF_COUNT_SW_TASK_CLOCK = 1, 82 PERF_COUNT_SW_PAGE_FAULTS = 2, 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 85 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 86 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 87 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 90 PERF_COUNT_SW_EMULATION_FAULTS = 8, 91 PERF_COUNT_SW_DUMMY = 9, 92 PERF_COUNT_SW_BPF_OUTPUT = 10, 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 PERF_COUNT_SW_MAX, 95 }; 96 enum perf_event_sample_format { 97 PERF_SAMPLE_IP = 1U << 0, 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 PERF_SAMPLE_TID = 1U << 1, 100 PERF_SAMPLE_TIME = 1U << 2, 101 PERF_SAMPLE_ADDR = 1U << 3, 102 PERF_SAMPLE_READ = 1U << 4, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 PERF_SAMPLE_CALLCHAIN = 1U << 5, 105 PERF_SAMPLE_ID = 1U << 6, 106 PERF_SAMPLE_CPU = 1U << 7, 107 PERF_SAMPLE_PERIOD = 1U << 8, 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 PERF_SAMPLE_STREAM_ID = 1U << 9, 110 PERF_SAMPLE_RAW = 1U << 10, 111 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 112 PERF_SAMPLE_REGS_USER = 1U << 12, 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 PERF_SAMPLE_STACK_USER = 1U << 13, 115 PERF_SAMPLE_WEIGHT = 1U << 14, 116 PERF_SAMPLE_DATA_SRC = 1U << 15, 117 PERF_SAMPLE_IDENTIFIER = 1U << 16, 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 PERF_SAMPLE_TRANSACTION = 1U << 17, 120 PERF_SAMPLE_REGS_INTR = 1U << 18, 121 PERF_SAMPLE_MAX = 1U << 19, 122 }; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 enum perf_branch_sample_type_shift { 125 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, 126 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, 127 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, 130 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, 131 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, 132 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, 135 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, 136 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, 137 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, 140 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, 141 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, 142 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, 145 PERF_SAMPLE_BRANCH_MAX_SHIFT 146 }; 147 enum perf_branch_sample_type { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 150 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 151 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 152 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 155 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 156 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 157 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 160 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 161 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 162 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 165 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 166 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 167 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 170 }; 171 #define PERF_SAMPLE_BRANCH_PLM_ALL (PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_HV) 172 enum perf_sample_regs_abi { 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 PERF_SAMPLE_REGS_ABI_NONE = 0, 175 PERF_SAMPLE_REGS_ABI_32 = 1, 176 PERF_SAMPLE_REGS_ABI_64 = 2, 177 }; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 enum { 180 PERF_TXN_ELISION = (1 << 0), 181 PERF_TXN_TRANSACTION = (1 << 1), 182 PERF_TXN_SYNC = (1 << 2), 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 PERF_TXN_ASYNC = (1 << 3), 185 PERF_TXN_RETRY = (1 << 4), 186 PERF_TXN_CONFLICT = (1 << 5), 187 PERF_TXN_CAPACITY_WRITE = (1 << 6), 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 PERF_TXN_CAPACITY_READ = (1 << 7), 190 PERF_TXN_MAX = (1 << 8), 191 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 192 PERF_TXN_ABORT_SHIFT = 32, 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 }; 195 enum perf_event_read_format { 196 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 197 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 PERF_FORMAT_ID = 1U << 2, 200 PERF_FORMAT_GROUP = 1U << 3, 201 PERF_FORMAT_MAX = 1U << 4, 202 }; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define PERF_ATTR_SIZE_VER0 64 205 #define PERF_ATTR_SIZE_VER1 72 206 #define PERF_ATTR_SIZE_VER2 80 207 #define PERF_ATTR_SIZE_VER3 96 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define PERF_ATTR_SIZE_VER4 104 210 #define PERF_ATTR_SIZE_VER5 112 211 struct perf_event_attr { 212 __u32 type; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 __u32 size; 215 __u64 config; 216 union { 217 __u64 sample_period; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u64 sample_freq; 220 }; 221 __u64 sample_type; 222 __u64 read_format; 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 __u64 disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, __reserved_1 : 36; 225 union { 226 __u32 wakeup_events; 227 __u32 wakeup_watermark; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 }; 230 __u32 bp_type; 231 union { 232 __u64 bp_addr; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 __u64 config1; 235 }; 236 union { 237 __u64 bp_len; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 __u64 config2; 240 }; 241 __u64 branch_sample_type; 242 __u64 sample_regs_user; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 __u32 sample_stack_user; 245 __s32 clockid; 246 __u64 sample_regs_intr; 247 __u32 aux_watermark; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 __u16 sample_max_stack; 250 __u16 __reserved_2; 251 }; 252 #define perf_flags(attr) (* (& (attr)->read_format + 1)) 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define PERF_EVENT_IOC_ENABLE _IO('$', 0) 255 #define PERF_EVENT_IOC_DISABLE _IO('$', 1) 256 #define PERF_EVENT_IOC_REFRESH _IO('$', 2) 257 #define PERF_EVENT_IOC_RESET _IO('$', 3) 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 260 #define PERF_EVENT_IOC_SET_OUTPUT _IO('$', 5) 261 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 262 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 265 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 266 enum perf_event_ioc_flags { 267 PERF_IOC_FLAG_GROUP = 1U << 0, 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 }; 270 struct perf_event_mmap_page { 271 __u32 version; 272 __u32 compat_version; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 __u32 lock; 275 __u32 index; 276 __s64 offset; 277 __u64 time_enabled; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 __u64 time_running; 280 union { 281 __u64 capabilities; 282 struct { 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 __u64 cap_bit0 : 1, cap_bit0_is_deprecated : 1, cap_user_rdpmc : 1, cap_user_time : 1, cap_user_time_zero : 1, cap_____res : 59; 285 }; 286 }; 287 __u16 pmc_width; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 __u16 time_shift; 290 __u32 time_mult; 291 __u64 time_offset; 292 __u64 time_zero; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 __u32 size; 295 __u8 __reserved[118 * 8 + 4]; 296 __u64 data_head; 297 __u64 data_tail; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 __u64 data_offset; 300 __u64 data_size; 301 __u64 aux_head; 302 __u64 aux_tail; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 __u64 aux_offset; 305 __u64 aux_size; 306 }; 307 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 310 #define PERF_RECORD_MISC_KERNEL (1 << 0) 311 #define PERF_RECORD_MISC_USER (2 << 0) 312 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 315 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 316 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 317 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 320 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 321 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 322 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 struct perf_event_header { 325 __u32 type; 326 __u16 misc; 327 __u16 size; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 }; 330 enum perf_event_type { 331 PERF_RECORD_MMAP = 1, 332 PERF_RECORD_LOST = 2, 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 PERF_RECORD_COMM = 3, 335 PERF_RECORD_EXIT = 4, 336 PERF_RECORD_THROTTLE = 5, 337 PERF_RECORD_UNTHROTTLE = 6, 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 PERF_RECORD_FORK = 7, 340 PERF_RECORD_READ = 8, 341 PERF_RECORD_SAMPLE = 9, 342 PERF_RECORD_MMAP2 = 10, 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 PERF_RECORD_AUX = 11, 345 PERF_RECORD_ITRACE_START = 12, 346 PERF_RECORD_LOST_SAMPLES = 13, 347 PERF_RECORD_SWITCH = 14, 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 PERF_RECORD_SWITCH_CPU_WIDE = 15, 350 PERF_RECORD_MAX, 351 }; 352 #define PERF_MAX_STACK_DEPTH 127 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 #define PERF_MAX_CONTEXTS_PER_STACK 8 355 enum perf_callchain_context { 356 PERF_CONTEXT_HV = (__u64) - 32, 357 PERF_CONTEXT_KERNEL = (__u64) - 128, 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 PERF_CONTEXT_USER = (__u64) - 512, 360 PERF_CONTEXT_GUEST = (__u64) - 2048, 361 PERF_CONTEXT_GUEST_KERNEL = (__u64) - 2176, 362 PERF_CONTEXT_GUEST_USER = (__u64) - 2560, 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 PERF_CONTEXT_MAX = (__u64) - 4095, 365 }; 366 #define PERF_AUX_FLAG_TRUNCATED 0x01 367 #define PERF_AUX_FLAG_OVERWRITE 0x02 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 370 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 371 #define PERF_FLAG_PID_CGROUP (1UL << 2) 372 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 union perf_mem_data_src { 375 __u64 val; 376 struct { 377 __u64 mem_op : 5, mem_lvl : 14, mem_snoop : 5, mem_lock : 2, mem_dtlb : 7, mem_rsvd : 31; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 }; 380 }; 381 #define PERF_MEM_OP_NA 0x01 382 #define PERF_MEM_OP_LOAD 0x02 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define PERF_MEM_OP_STORE 0x04 385 #define PERF_MEM_OP_PFETCH 0x08 386 #define PERF_MEM_OP_EXEC 0x10 387 #define PERF_MEM_OP_SHIFT 0 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define PERF_MEM_LVL_NA 0x01 390 #define PERF_MEM_LVL_HIT 0x02 391 #define PERF_MEM_LVL_MISS 0x04 392 #define PERF_MEM_LVL_L1 0x08 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define PERF_MEM_LVL_LFB 0x10 395 #define PERF_MEM_LVL_L2 0x20 396 #define PERF_MEM_LVL_L3 0x40 397 #define PERF_MEM_LVL_LOC_RAM 0x80 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define PERF_MEM_LVL_REM_RAM1 0x100 400 #define PERF_MEM_LVL_REM_RAM2 0x200 401 #define PERF_MEM_LVL_REM_CCE1 0x400 402 #define PERF_MEM_LVL_REM_CCE2 0x800 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define PERF_MEM_LVL_IO 0x1000 405 #define PERF_MEM_LVL_UNC 0x2000 406 #define PERF_MEM_LVL_SHIFT 5 407 #define PERF_MEM_SNOOP_NA 0x01 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define PERF_MEM_SNOOP_NONE 0x02 410 #define PERF_MEM_SNOOP_HIT 0x04 411 #define PERF_MEM_SNOOP_MISS 0x08 412 #define PERF_MEM_SNOOP_HITM 0x10 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define PERF_MEM_SNOOP_SHIFT 19 415 #define PERF_MEM_LOCK_NA 0x01 416 #define PERF_MEM_LOCK_LOCKED 0x02 417 #define PERF_MEM_LOCK_SHIFT 24 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define PERF_MEM_TLB_NA 0x01 420 #define PERF_MEM_TLB_HIT 0x02 421 #define PERF_MEM_TLB_MISS 0x04 422 #define PERF_MEM_TLB_L1 0x08 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define PERF_MEM_TLB_L2 0x10 425 #define PERF_MEM_TLB_WK 0x20 426 #define PERF_MEM_TLB_OS 0x40 427 #define PERF_MEM_TLB_SHIFT 26 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define PERF_MEM_S(a,s) (((__u64) PERF_MEM_ ##a ##_ ##s) << PERF_MEM_ ##a ##_SHIFT) 430 struct perf_branch_entry { 431 __u64 from; 432 __u64 to; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 __u64 mispred : 1, predicted : 1, in_tx : 1, abort : 1, cycles : 16, reserved : 44; 435 }; 436 #endif 437
