1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef MLX5_ABI_USER_H 20 #define MLX5_ABI_USER_H 21 #include <linux/types.h> 22 enum { 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 25 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 26 }; 27 enum { 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 30 }; 31 enum { 32 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 }; 35 #define MLX5_IB_UVERBS_ABI_VERSION 1 36 struct mlx5_ib_alloc_ucontext_req { 37 __u32 total_num_uuars; 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 __u32 num_low_latency_uuars; 40 }; 41 struct mlx5_ib_alloc_ucontext_req_v2 { 42 __u32 total_num_uuars; 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 __u32 num_low_latency_uuars; 45 __u32 flags; 46 __u32 comp_mask; 47 __u8 max_cqe_version; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 __u8 reserved0; 50 __u16 reserved1; 51 __u32 reserved2; 52 }; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 enum mlx5_ib_alloc_ucontext_resp_mask { 55 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 56 }; 57 enum mlx5_user_cmds_supp_uhw { 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 60 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 61 }; 62 struct mlx5_ib_alloc_ucontext_resp { 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 __u32 qp_tab_size; 65 __u32 bf_reg_size; 66 __u32 tot_uuars; 67 __u32 cache_line_size; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 __u16 max_sq_desc_sz; 70 __u16 max_rq_desc_sz; 71 __u32 max_send_wqebb; 72 __u32 max_recv_wr; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 __u32 max_srq_recv_wr; 75 __u16 num_ports; 76 __u16 reserved1; 77 __u32 comp_mask; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 __u32 response_length; 80 __u8 cqe_version; 81 __u8 cmds_supp_uhw; 82 __u16 reserved2; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 __u64 hca_core_clock_offset; 85 }; 86 struct mlx5_ib_alloc_pd_resp { 87 __u32 pdn; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 }; 90 struct mlx5_ib_tso_caps { 91 __u32 max_tso; 92 __u32 supported_qpts; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 }; 95 struct mlx5_ib_rss_caps { 96 __u64 rx_hash_fields_mask; 97 __u8 rx_hash_function; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u8 reserved[7]; 100 }; 101 enum mlx5_ib_cqe_comp_res_format { 102 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 105 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 106 }; 107 struct mlx5_ib_cqe_comp_caps { 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 __u32 max_num; 110 __u32 supported_format; 111 }; 112 struct mlx5_packet_pacing_caps { 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 qp_rate_limit_min; 115 __u32 qp_rate_limit_max; 116 __u32 supported_qpts; 117 __u32 reserved; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 }; 120 struct mlx5_ib_query_device_resp { 121 __u32 comp_mask; 122 __u32 response_length; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 struct mlx5_ib_tso_caps tso_caps; 125 struct mlx5_ib_rss_caps rss_caps; 126 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 127 struct mlx5_packet_pacing_caps packet_pacing_caps; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 __u32 mlx5_ib_support_multi_pkt_send_wqes; 130 __u32 reserved; 131 }; 132 struct mlx5_ib_create_cq { 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __u64 buf_addr; 135 __u64 db_addr; 136 __u32 cqe_size; 137 __u8 cqe_comp_en; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 __u8 cqe_comp_res_format; 140 __u16 reserved; 141 }; 142 struct mlx5_ib_create_cq_resp { 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 __u32 cqn; 145 __u32 reserved; 146 }; 147 struct mlx5_ib_resize_cq { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 __u64 buf_addr; 150 __u16 cqe_size; 151 __u16 reserved0; 152 __u32 reserved1; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 }; 155 struct mlx5_ib_create_srq { 156 __u64 buf_addr; 157 __u64 db_addr; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 __u32 flags; 160 __u32 reserved0; 161 __u32 uidx; 162 __u32 reserved1; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 }; 165 struct mlx5_ib_create_srq_resp { 166 __u32 srqn; 167 __u32 reserved; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 }; 170 struct mlx5_ib_create_qp { 171 __u64 buf_addr; 172 __u64 db_addr; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 __u32 sq_wqe_count; 175 __u32 rq_wqe_count; 176 __u32 rq_wqe_shift; 177 __u32 flags; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 __u32 uidx; 180 __u32 reserved0; 181 __u64 sq_buf_addr; 182 }; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 enum mlx5_rx_hash_function_flags { 185 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 186 }; 187 enum mlx5_rx_hash_fields { 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 190 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 191 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 192 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 195 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 196 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 197 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 }; 200 struct mlx5_ib_create_qp_rss { 201 __u64 rx_hash_fields_mask; 202 __u8 rx_hash_function; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 __u8 rx_key_len; 205 __u8 reserved[6]; 206 __u8 rx_hash_key[128]; 207 __u32 comp_mask; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __u32 reserved1; 210 }; 211 struct mlx5_ib_create_qp_resp { 212 __u32 uuar_index; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 }; 215 struct mlx5_ib_alloc_mw { 216 __u32 comp_mask; 217 __u8 num_klms; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u8 reserved1; 220 __u16 reserved2; 221 }; 222 struct mlx5_ib_create_wq { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 __u64 buf_addr; 225 __u64 db_addr; 226 __u32 rq_wqe_count; 227 __u32 rq_wqe_shift; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 __u32 user_index; 230 __u32 flags; 231 __u32 comp_mask; 232 __u32 reserved; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 }; 235 struct mlx5_ib_create_ah_resp { 236 __u32 response_length; 237 __u8 dmac[ETH_ALEN]; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 __u8 reserved[6]; 240 }; 241 struct mlx5_ib_create_wq_resp { 242 __u32 response_length; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 __u32 reserved; 245 }; 246 struct mlx5_ib_create_rwq_ind_tbl_resp { 247 __u32 response_length; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 __u32 reserved; 250 }; 251 struct mlx5_ib_modify_wq { 252 __u32 comp_mask; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 __u32 reserved; 255 }; 256 #endif 257
