1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ASM_MIPS_BOARDS_GENERIC_H 20 #define __ASM_MIPS_BOARDS_GENERIC_H 21 #include <asm/addrspace.h> 22 #include <asm/byteorder.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <asm/mips-boards/bonito64.h> 25 #define ASCII_DISPLAY_WORD_BASE 0x1f000410 26 #define ASCII_DISPLAY_POS_BASE 0x1f000418 27 #define YAMON_PROM_PRINT_ADDR 0x1fc00504 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define SOFTRES_REG 0x1f000500 30 #define GORESET 0x42 31 #define MIPS_REVISION_REG 0x1fc00010 32 #define MIPS_REVISION_CORID_QED_RM5261 0 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MIPS_REVISION_CORID_CORE_LV 1 35 #define MIPS_REVISION_CORID_BONITO64 2 36 #define MIPS_REVISION_CORID_CORE_20K 3 37 #define MIPS_REVISION_CORID_CORE_FPGA 4 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define MIPS_REVISION_CORID_CORE_MSC 5 40 #define MIPS_REVISION_CORID_CORE_EMUL 6 41 #define MIPS_REVISION_CORID_CORE_FPGA2 7 42 #define MIPS_REVISION_CORID_CORE_FPGAR2 8 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MIPS_REVISION_CORID_CORE_FPGA3 9 45 #define MIPS_REVISION_CORID_CORE_24K 10 46 #define MIPS_REVISION_CORID_CORE_FPGA4 11 47 #define MIPS_REVISION_CORID_CORE_FPGA5 12 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 50 #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 51 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 52 #define MIPS_REVISION_SCON_OTHER 0 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define MIPS_REVISION_SCON_SOCITSC 1 55 #define MIPS_REVISION_SCON_SOCITSCP 2 56 #define MIPS_REVISION_SCON_UNKNOWN -1 57 #define MIPS_REVISION_SCON_GT64120 -2 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define MIPS_REVISION_SCON_BONITO -3 60 #define MIPS_REVISION_SCON_BRTL -4 61 #define MIPS_REVISION_SCON_SOCIT -5 62 #define MIPS_REVISION_SCON_ROCIT -6 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 65 #define mips_pcibios_init() do { } while (0) 66 #endif 67
