1 /************************************************************************** 2 * Copyright (c) 2007, Intel Corporation. 3 * All Rights Reserved. 4 * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA. 5 * All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 **************************************************************************/ 21 22 #ifndef _PSB_DRM_H_ 23 #define _PSB_DRM_H_ 24 25 #if defined(__linux__) && !defined(__KERNEL__) 26 #include <stdbool.h> 27 #include <stdint.h> 28 #include <linux/types.h> 29 #include "drm_mode.h" 30 #endif 31 32 33 34 /* 35 * Menlow/MRST graphics driver package version 36 * a.b.c.xxxx 37 * a - Product Family: 5 - Linux 38 * b - Major Release Version: 0 - non-Gallium (Unbuntu) 39 * 1 - Gallium (Moblin2) 40 * 2 - IMG (Moblin2) 41 * 3 - IMG (Meego) 42 * 4 - IMG (Android) 43 * c - Hotfix Release 44 * xxxx - Graphics internal build # 45 */ 46 #define PSB_PACKAGE_VERSION "5.6.0.1202" 47 48 #define DRM_PSB_SAREA_MAJOR 0 49 #define DRM_PSB_SAREA_MINOR 2 50 #define PSB_FIXED_SHIFT 16 51 52 #define PSB_NUM_PIPE 3 53 54 /* 55 * Public memory types. 56 */ 57 58 #define DRM_PSB_MEM_MMU TTM_PL_PRIV1 59 #define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1 60 61 #define TTM_PL_CI TTM_PL_PRIV0 62 #define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0 63 #define TTM_PL_RAR TTM_PL_PRIV2 64 #define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2 65 #define TTM_PL_IMR TTM_PL_PRIV2 66 #define TTM_PL_FLAG_IMR TTM_PL_FLAG_PRIV2 67 68 #define DRM_PSB_MEM_MMU_TILING TTM_PL_PRIV3 69 #define DRM_PSB_FLAG_MEM_MMU_TILING TTM_PL_FLAG_PRIV3 70 71 72 /*Status of the command sent to the gfx device.*/ 73 typedef enum { 74 DRM_CMD_SUCCESS, 75 DRM_CMD_FAILED, 76 DRM_CMD_HANG 77 } drm_cmd_status_t; 78 79 struct drm_psb_scanout { 80 uint32_t buffer_id; /* DRM buffer object ID */ 81 uint32_t rotation; /* Rotation as in RR_rotation definitions */ 82 uint32_t stride; /* Buffer stride in bytes */ 83 uint32_t depth; /* Buffer depth in bits (NOT) bpp */ 84 uint32_t width; /* Buffer width in pixels */ 85 uint32_t height; /* Buffer height in lines */ 86 int32_t transform[3][3]; /* Buffer composite transform */ 87 /* (scaling, rot, reflect) */ 88 }; 89 90 #define DRM_PSB_SAREA_OWNERS 16 91 #define DRM_PSB_SAREA_OWNER_2D 0 92 #define DRM_PSB_SAREA_OWNER_3D 1 93 #define DRM_PSB_SAREA_SCANOUTS 3 94 95 struct drm_psb_sarea { 96 /* Track changes of this data structure */ 97 98 uint32_t major; 99 uint32_t minor; 100 101 /* Last context to touch part of hw */ 102 uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; 103 104 /* Definition of front- and rotated buffers */ 105 uint32_t num_scanouts; 106 struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; 107 108 int planeA_x; 109 int planeA_y; 110 int planeA_w; 111 int planeA_h; 112 int planeB_x; 113 int planeB_y; 114 int planeB_w; 115 int planeB_h; 116 /* Number of active scanouts */ 117 uint32_t num_active_scanouts; 118 }; 119 120 #define PSB_RELOC_MAGIC 0x67676767 121 #define PSB_RELOC_SHIFT_MASK 0x0000FFFF 122 #define PSB_RELOC_SHIFT_SHIFT 0 123 #define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 124 #define PSB_RELOC_ALSHIFT_SHIFT 16 125 126 /* Offset of the indicated buffer*/ 127 #define PSB_RELOC_OP_OFFSET 0 128 129 struct drm_psb_reloc { 130 uint32_t reloc_op; 131 uint32_t where; /* offset in destination buffer */ 132 uint32_t buffer; /* Buffer reloc applies to */ 133 uint32_t mask; /* Destination format: */ 134 uint32_t shift; /* Destination format: */ 135 uint32_t pre_add; /* Destination format: */ 136 uint32_t background; /* Destination add */ 137 uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */ 138 uint32_t arg0; /* Reloc-op dependant */ 139 uint32_t arg1; 140 }; 141 142 143 #define PSB_GPU_ACCESS_READ (1ULL << 32) 144 #define PSB_GPU_ACCESS_WRITE (1ULL << 33) 145 #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) 146 147 #define PSB_BO_FLAG_COMMAND (1ULL << 52) 148 149 #define PSB_ENGINE_2D 2 150 #define PSB_ENGINE_DECODE 0 151 #define PSB_ENGINE_VIDEO 0 152 #define LNC_ENGINE_ENCODE 1 153 #ifdef MERRIFIELD 154 #define PSB_NUM_ENGINES 7 155 #else 156 #define PSB_NUM_ENGINES 2 157 #endif 158 #define VSP_ENGINE_VPP 6 159 160 /* 161 * For this fence class we have a couple of 162 * fence types. 163 */ 164 165 #define _PSB_FENCE_EXE_SHIFT 0 166 #define _PSB_FENCE_FEEDBACK_SHIFT 4 167 168 #define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT) 169 #define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) 170 171 #define PSB_FEEDBACK_OP_VISTEST (1 << 0) 172 173 struct drm_psb_extension_rep { 174 int32_t exists; 175 uint32_t driver_ioctl_offset; 176 uint32_t sarea_offset; 177 uint32_t major; 178 uint32_t minor; 179 uint32_t pl; 180 }; 181 182 #define DRM_PSB_EXT_NAME_LEN 128 183 184 union drm_psb_extension_arg { 185 char extension[DRM_PSB_EXT_NAME_LEN]; 186 struct drm_psb_extension_rep rep; 187 }; 188 189 #define PSB_NOT_FENCE (1 << 0) 190 #define PSB_MEM_CLFLUSH (1 << 1) 191 192 struct psb_validate_req { 193 uint64_t set_flags; 194 uint64_t clear_flags; 195 uint64_t next; 196 uint64_t presumed_gpu_offset; 197 uint32_t buffer_handle; 198 uint32_t presumed_flags; 199 uint32_t pad64; 200 uint32_t unfence_flag; 201 }; 202 203 struct psb_validate_rep { 204 uint64_t gpu_offset; 205 uint32_t placement; 206 uint32_t fence_type_mask; 207 }; 208 209 #define PSB_USE_PRESUMED (1 << 0) 210 211 struct psb_validate_arg { 212 uint64_t handled; 213 uint64_t ret; 214 union { 215 struct psb_validate_req req; 216 struct psb_validate_rep rep; 217 } d; 218 }; 219 220 221 #define DRM_PSB_FENCE_NO_USER (1 << 0) 222 223 struct psb_ttm_fence_rep { 224 uint32_t handle; 225 uint32_t fence_class; 226 uint32_t fence_type; 227 uint32_t signaled_types; 228 uint32_t error; 229 }; 230 231 typedef struct drm_psb_cmdbuf_arg { 232 uint64_t buffer_list; /* List of buffers to validate */ 233 uint64_t fence_arg; 234 235 uint32_t cmdbuf_handle; /* 2D Command buffer object or, */ 236 uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */ 237 uint32_t cmdbuf_size; 238 239 uint32_t reloc_handle; /* Reloc buffer object */ 240 uint32_t reloc_offset; 241 uint32_t num_relocs; 242 243 /* Not implemented yet */ 244 uint32_t fence_flags; 245 uint32_t engine; 246 247 } drm_psb_cmdbuf_arg_t; 248 249 typedef struct drm_psb_pageflip_arg { 250 uint32_t flip_offset; 251 uint32_t stride; 252 } drm_psb_pageflip_arg_t; 253 254 typedef enum { 255 LNC_VIDEO_DEVICE_INFO, 256 LNC_VIDEO_GETPARAM_IMR_INFO, 257 LNC_VIDEO_GETPARAM_CI_INFO, 258 LNC_VIDEO_FRAME_SKIP, 259 IMG_VIDEO_DECODE_STATUS, 260 IMG_VIDEO_NEW_CONTEXT, 261 IMG_VIDEO_RM_CONTEXT, 262 IMG_VIDEO_UPDATE_CONTEXT, 263 IMG_VIDEO_MB_ERROR, 264 IMG_VIDEO_SET_DISPLAYING_FRAME, 265 IMG_VIDEO_GET_DISPLAYING_FRAME, 266 IMG_VIDEO_GET_HDMI_STATE, 267 IMG_VIDEO_SET_HDMI_STATE, 268 PNW_VIDEO_QUERY_ENTRY, 269 IMG_DISPLAY_SET_WIDI_EXT_STATE, 270 IMG_VIDEO_IED_STATE 271 } lnc_getparam_key_t; 272 273 struct drm_lnc_video_getparam_arg { 274 uint64_t key; 275 uint64_t arg; /* argument pointer */ 276 uint64_t value; /* feed back pointer */ 277 }; 278 279 struct drm_video_displaying_frameinfo { 280 uint32_t buf_handle; 281 uint32_t width; 282 uint32_t height; 283 uint32_t size; /* buffer size */ 284 uint32_t format; /* fourcc */ 285 uint32_t luma_stride; /* luma stride */ 286 uint32_t chroma_u_stride; /* chroma stride */ 287 uint32_t chroma_v_stride; 288 uint32_t luma_offset; /* luma offset from the beginning of the memory */ 289 uint32_t chroma_u_offset; /* UV offset from the beginning of the memory */ 290 uint32_t chroma_v_offset; 291 uint32_t reserved; 292 }; 293 294 /* 295 * Feedback components: 296 */ 297 298 /* 299 * Vistest component. The number of these in the feedback buffer 300 * equals the number of vistest breakpoints + 1. 301 * This is currently the only feedback component. 302 */ 303 304 struct drm_psb_vistest { 305 uint32_t vt[8]; 306 }; 307 308 struct drm_psb_sizes_arg { 309 uint32_t ta_mem_size; 310 uint32_t mmu_size; 311 uint32_t pds_size; 312 uint32_t rastgeom_size; 313 uint32_t tt_size; 314 uint32_t vram_size; 315 }; 316 317 struct drm_psb_hist_status_arg { 318 uint32_t buf[32]; 319 }; 320 321 struct drm_psb_dpst_lut_arg { 322 uint8_t lut[256]; 323 int output_id; 324 }; 325 326 struct mrst_timing_info { 327 uint16_t pixel_clock; 328 uint8_t hactive_lo; 329 uint8_t hblank_lo; 330 uint8_t hblank_hi:4; 331 uint8_t hactive_hi:4; 332 uint8_t vactive_lo; 333 uint8_t vblank_lo; 334 uint8_t vblank_hi:4; 335 uint8_t vactive_hi:4; 336 uint8_t hsync_offset_lo; 337 uint8_t hsync_pulse_width_lo; 338 uint8_t vsync_pulse_width_lo:4; 339 uint8_t vsync_offset_lo:4; 340 uint8_t vsync_pulse_width_hi:2; 341 uint8_t vsync_offset_hi:2; 342 uint8_t hsync_pulse_width_hi:2; 343 uint8_t hsync_offset_hi:2; 344 uint8_t width_mm_lo; 345 uint8_t height_mm_lo; 346 uint8_t height_mm_hi:4; 347 uint8_t width_mm_hi:4; 348 uint8_t hborder; 349 uint8_t vborder; 350 uint8_t unknown0:1; 351 uint8_t hsync_positive:1; 352 uint8_t vsync_positive:1; 353 uint8_t separate_sync:2; 354 uint8_t stereo:1; 355 uint8_t unknown6:1; 356 uint8_t interlaced:1; 357 } __attribute__((packed)); 358 359 struct gct_r10_timing_info { 360 uint16_t pixel_clock; 361 uint32_t hactive_lo:8; 362 uint32_t hactive_hi:4; 363 uint32_t hblank_lo:8; 364 uint32_t hblank_hi:4; 365 uint32_t hsync_offset_lo:8; 366 uint16_t hsync_offset_hi:2; 367 uint16_t hsync_pulse_width_lo:8; 368 uint16_t hsync_pulse_width_hi:2; 369 uint16_t hsync_positive:1; 370 uint16_t rsvd_1:3; 371 uint8_t vactive_lo:8; 372 uint16_t vactive_hi:4; 373 uint16_t vblank_lo:8; 374 uint16_t vblank_hi:4; 375 uint16_t vsync_offset_lo:4; 376 uint16_t vsync_offset_hi:2; 377 uint16_t vsync_pulse_width_lo:4; 378 uint16_t vsync_pulse_width_hi:2; 379 uint16_t vsync_positive:1; 380 uint16_t rsvd_2:3; 381 } __attribute__((packed)); 382 383 struct mrst_panel_descriptor_v1 { 384 uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 385 /* 0x61190 if MIPI */ 386 uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 387 uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 388 uint32_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */ 389 /* Register 0x61210 */ 390 struct mrst_timing_info DTD;/*18 bytes, Standard definition */ 391 uint16_t Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */ 392 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */ 393 /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */ 394 uint16_t Panel_MIPI_Display_Descriptor; 395 /*16 bits, Defined as follows: */ 396 /* if MIPI, 0x0000 if LVDS */ 397 /* Bit 0, Type, 2 bits, */ 398 /* 0: Type-1, */ 399 /* 1: Type-2, */ 400 /* 2: Type-3, */ 401 /* 3: Type-4 */ 402 /* Bit 2, Pixel Format, 4 bits */ 403 /* Bit0: 16bpp (not supported in LNC), */ 404 /* Bit1: 18bpp loosely packed, */ 405 /* Bit2: 18bpp packed, */ 406 /* Bit3: 24bpp */ 407 /* Bit 6, Reserved, 2 bits, 00b */ 408 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 409 /* Bit 14, Reserved, 2 bits, 00b */ 410 } __attribute__((packed)); 411 412 struct mrst_panel_descriptor_v2 { 413 uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 414 /* 0x61190 if MIPI */ 415 uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 416 uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 417 uint8_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */ 418 /* Register 0x61210 */ 419 struct mrst_timing_info DTD;/*18 bytes, Standard definition */ 420 uint16_t Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/ 421 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/ 422 uint8_t Panel_Initial_Brightness;/* [7:0] 0 - 100% */ 423 /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/ 424 uint16_t Panel_MIPI_Display_Descriptor; 425 /*16 bits, Defined as follows: */ 426 /* if MIPI, 0x0000 if LVDS */ 427 /* Bit 0, Type, 2 bits, */ 428 /* 0: Type-1, */ 429 /* 1: Type-2, */ 430 /* 2: Type-3, */ 431 /* 3: Type-4 */ 432 /* Bit 2, Pixel Format, 4 bits */ 433 /* Bit0: 16bpp (not supported in LNC), */ 434 /* Bit1: 18bpp loosely packed, */ 435 /* Bit2: 18bpp packed, */ 436 /* Bit3: 24bpp */ 437 /* Bit 6, Reserved, 2 bits, 00b */ 438 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 439 /* Bit 14, Reserved, 2 bits, 00b */ 440 } __attribute__((packed)); 441 442 union mrst_panel_rx { 443 struct { 444 uint16_t NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ 445 /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ 446 uint16_t MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ 447 /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/ 448 uint16_t SupportedVideoTransferMode:2; /*0: Non-burst only */ 449 /* 1: Burst and non-burst */ 450 /* 2/3: Reserved */ 451 uint16_t HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/ 452 uint16_t DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/ 453 uint16_t ECC_ChecksumCapabilities:1; /*1 bit,0: No, 1: Yes*/ 454 uint16_t BidirectionalCommunication:1; /*1 bit,0: No, 1: Yes */ 455 uint16_t Rsvd:5; /*5 bits,00000b */ 456 } panelrx; 457 uint16_t panel_receiver; 458 } __attribute__((packed)); 459 460 struct gct_ioctl_arg { 461 uint8_t bpi; /* boot panel index, number of panel used during boot */ 462 uint8_t pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */ 463 struct mrst_timing_info DTD; /* timing info for the selected panel */ 464 uint32_t Panel_Port_Control; 465 uint32_t PP_On_Sequencing;/*1 dword,Register 0x61208,*/ 466 uint32_t PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 467 uint32_t PP_Cycle_Delay; 468 uint16_t Panel_Backlight_Inverter_Descriptor; 469 uint16_t Panel_MIPI_Display_Descriptor; 470 } __attribute__((packed)); 471 472 473 struct gct_timing_desc_block { 474 uint16_t clock; 475 uint16_t hactive:12; 476 uint16_t hblank:12; 477 uint16_t hsync_start:10; 478 uint16_t hsync_end:10; 479 uint16_t hsync_polarity:1; 480 uint16_t h_reversed:3; 481 uint16_t vactive:12; 482 uint16_t vblank:12; 483 uint16_t vsync_start:6; 484 uint16_t vsync_end:6; 485 uint16_t vsync_polarity:1; 486 uint16_t v_reversed:3; 487 } __packed; 488 489 struct gct_display_desc_block { 490 uint8_t type:2; 491 uint8_t pxiel_format:4; 492 uint8_t mode:2; 493 uint8_t frame_rate:6; 494 uint8_t reserved:2; 495 } __attribute__((packed)); 496 497 struct gct_dsi_desc_block { 498 uint8_t lane_count:2; 499 uint8_t lane_frequency:3; 500 uint8_t transfer_mode:2; 501 uint8_t hs_clock_behavior:1; 502 uint8_t duo_display_support:1; 503 uint8_t ecc_caps:1; 504 uint8_t bdirect_support:1; 505 uint8_t reversed:5; 506 } __packed; 507 508 struct gct_bkl_desc_block { 509 uint16_t frequency; 510 uint8_t max_brightness:7; 511 uint8_t polarity:1; 512 } __packed; 513 514 struct gct_r20_clock_desc { 515 uint8_t pre_divisor:2; 516 uint16_t divisor:9; 517 uint8_t post_divisor:4; 518 uint8_t pll_bypass:1; 519 uint8_t cck_clock_divisor:1; 520 uint8_t reserved:7; 521 } __packed; 522 523 struct gct_r20_panel_info { 524 uint16_t width; 525 uint16_t height; 526 } __packed; 527 528 struct gct_r20_panel_mode { 529 uint8_t mode:1; 530 uint16_t reserved:15; 531 } __packed; 532 533 struct gct_r20_dsi_desc { 534 uint8_t num_dsi_lanes:2; 535 uint16_t reserved:14; 536 } __packed; 537 538 struct gct_r20_panel_desc { 539 uint8_t panel_name[16]; 540 struct gct_timing_desc_block timing; 541 struct gct_r20_clock_desc clock_desc; 542 struct gct_r20_panel_info panel_info; 543 struct gct_r20_panel_mode panel_mode; 544 struct gct_r20_dsi_desc dsi_desc; 545 uint32_t early_init_seq; 546 uint32_t late_init_seq; 547 } __packed; 548 549 struct gct_r11_panel_desc { 550 uint8_t panel_name[16]; 551 struct gct_timing_desc_block timing; 552 struct gct_display_desc_block display; 553 struct gct_dsi_desc_block dsi; 554 struct gct_bkl_desc_block bkl; 555 uint32_t early_init_seq; 556 uint32_t late_init_seq; 557 } __packed; 558 559 struct gct_r10_panel_desc { 560 struct gct_timing_desc_block timing; 561 struct gct_display_desc_block display; 562 struct gct_dsi_desc_block dsi; 563 struct gct_bkl_desc_block bkl; 564 uint32_t early_init_seq; 565 uint32_t late_init_seq; 566 uint8_t reversed[4]; 567 } __packed; 568 569 struct intel_mid_vbt { 570 char signature[4]; /*4 bytes,"$GCT" */ 571 uint8_t revision; /*1 byte GCT version*/ 572 uint8_t checksum; /*1 byte checksum*/ 573 uint16_t size; /*2 byte size of checksumed data*/ 574 uint8_t num_of_panel_desc; /*1 byte number of panel descriptor*/ 575 uint8_t primary_panel_idx; /*1 byte primary panel descriptor idx*/ 576 uint8_t secondary_panel_idx; /*1 byte secondary panel desc idx*/ 577 uint8_t splash_flag; /*1 byte bit 0 is to disable splash*/ 578 uint8_t reserved[4]; /*[0..1] relates to GPU burst for R20*/ 579 void *panel_descs; 580 } __packed; 581 582 struct mrst_vbt { 583 char Signature[4]; /*4 bytes,"$GCT" */ 584 uint8_t Revision; /*1 byte */ 585 uint8_t Size; /*1 byte */ 586 uint8_t Checksum; /*1 byte,Calculated */ 587 void *mrst_gct; 588 } __attribute__ ((packed)); 589 590 struct mrst_gct_v1 { /* expect this table to change per customer request*/ 591 union { /*8 bits,Defined as follows: */ 592 struct { 593 uint8_t PanelType:4; /*4 bits, Bit field for panels*/ 594 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 595 /*2 bits,Specifies which of the*/ 596 uint8_t BootPanelIndex:2; 597 /* 4 panels to use by default*/ 598 uint8_t BootMIPI_DSI_RxIndex:2; /*Specifies which of*/ 599 /* the 4 MIPI DSI receivers to use*/ 600 } PD; 601 uint8_t PanelDescriptor; 602 }; 603 struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ 604 union mrst_panel_rx panelrx[4]; /* panel receivers*/ 605 } __attribute__((packed)); 606 607 struct mrst_gct_v2 { /* expect this table to change per customer request*/ 608 union { /*8 bits,Defined as follows: */ 609 struct { 610 uint8_t PanelType:4; /*4 bits, Bit field for panels*/ 611 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 612 /*2 bits,Specifies which of the*/ 613 uint8_t BootPanelIndex:2; 614 /* 4 panels to use by default*/ 615 uint8_t BootMIPI_DSI_RxIndex:2; /*Specifies which of*/ 616 /* the 4 MIPI DSI receivers to use*/ 617 } PD; 618 uint8_t PanelDescriptor; 619 }; 620 struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ 621 union mrst_panel_rx panelrx[4]; /* panel receivers*/ 622 } __attribute__((packed)); 623 624 #define PSB_DC_CRTC_SAVE 0x01 625 #define PSB_DC_CRTC_RESTORE 0x02 626 #define PSB_DC_OUTPUT_SAVE 0x04 627 #define PSB_DC_OUTPUT_RESTORE 0x08 628 #define PSB_DC_CRTC_MASK 0x03 629 #define PSB_DC_OUTPUT_MASK 0x0C 630 631 struct drm_psb_dc_state_arg { 632 uint32_t flags; 633 uint32_t obj_id; 634 }; 635 636 struct drm_psb_mode_operation_arg { 637 uint32_t obj_id; 638 uint16_t operation; 639 struct drm_mode_modeinfo mode; 640 void *data; 641 }; 642 643 struct drm_psb_stolen_memory_arg { 644 uint32_t base; 645 uint32_t size; 646 }; 647 648 /*Display Register Bits*/ 649 #define REGRWBITS_PFIT_CONTROLS (1 << 0) 650 #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1) 651 #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2) 652 #define REGRWBITS_PIPEASRC (1 << 3) 653 #define REGRWBITS_PIPEBSRC (1 << 4) 654 #define REGRWBITS_VTOTAL_A (1 << 5) 655 #define REGRWBITS_VTOTAL_B (1 << 6) 656 #define REGRWBITS_DSPACNTR (1 << 8) 657 #define REGRWBITS_DSPBCNTR (1 << 9) 658 #define REGRWBITS_DSPCCNTR (1 << 10) 659 #define REGRWBITS_SPRITE_UPDATE (1 << 11) 660 #define REGRWBITS_PIPEASTAT (1 << 12) 661 #define REGRWBITS_INT_MASK (1 << 13) 662 #define REGRWBITS_INT_ENABLE (1 << 14) 663 #define REGRWBITS_DISPLAY_ALL (1 << 15) 664 /*Overlay Register Bits*/ 665 #define OV_REGRWBITS_OVADD (1 << 0) 666 #define OV_REGRWBITS_OGAM_ALL (1 << 1) 667 668 #define OVC_REGRWBITS_OVADD (1 << 2) 669 #define OVC_REGRWBITS_OGAM_ALL (1 << 3) 670 671 #define OV_REGRWBITS_WAIT_FLIP (1 << 4) 672 #define OVC_REGRWBITS_WAIT_FLIP (1 << 5) 673 #define OVSTATUS_REGRBIT_OVR_UPDT (1 << 6) 674 675 /*sprite update fields*/ 676 #define SPRITE_UPDATE_SURFACE (0x00000001UL) 677 #define SPRITE_UPDATE_CONTROL (0x00000002UL) 678 #define SPRITE_UPDATE_POSITION (0x00000004UL) 679 #define SPRITE_UPDATE_SIZE (0x00000008UL) 680 #define SPRITE_UPDATE_WAIT_VBLANK (0X00000010UL) 681 #define SPRITE_UPDATE_CONSTALPHA (0x00000020UL) 682 #define SPRITE_UPDATE_ALL (0x0000003fUL) 683 684 /*vsync operation*/ 685 #define VSYNC_ENABLE (1 << 0) 686 #define VSYNC_DISABLE (1 << 1) 687 #define VSYNC_WAIT (1 << 2) 688 #define GET_VSYNC_COUNT (1 << 3) 689 struct intel_overlay_context { 690 uint32_t index; 691 uint32_t pipe; 692 uint32_t ovadd; 693 }; 694 695 struct intel_sprite_context { 696 uint32_t update_mask; 697 /*plane index 0-A, 1-B, 2-C,etc*/ 698 uint32_t index; 699 uint32_t pipe; 700 701 uint32_t cntr; 702 uint32_t linoff; 703 uint32_t stride; 704 uint32_t pos; 705 uint32_t size; 706 uint32_t keyminval; 707 uint32_t keymask; 708 uint32_t surf; 709 uint32_t keymaxval; 710 uint32_t tileoff; 711 uint32_t contalpa; 712 }; 713 714 /* dependent macros*/ 715 #define INTEL_SPRITE_PLANE_NUM 3 716 #define INTEL_OVERLAY_PLANE_NUM 2 717 #define INTEL_DISPLAY_PLANE_NUM 5 718 /* Medfield */ 719 #define INTEL_MDFLD_SPRITE_PLANE_NUM 3 720 #define INTEL_MDFLD_OVERLAY_PLANE_NUM 2 721 #define INTEL_MDFLD_CURSOR_PLANE_NUM 3 722 #define INTEL_MDFLD_DISPLAY_PLANE_NUM 8 723 #define INTEL_MDFLD_DISPLAY_PIPE_NUM 3 724 /* Clovertrail+ */ 725 #define INTEL_CTP_SPRITE_PLANE_NUM 2 726 #define INTEL_CTP_OVERLAY_PLANE_NUM 1 727 #define INTEL_CTP_CURSOR_PLANE_NUM 2 728 #define INTEL_CTP_DISPLAY_PLANE_NUM 5 729 #define INTEL_CTP_DISPLAY_PIPE_NUM 2 730 731 #define INVALID_INDEX 0xffffffff 732 733 struct mdfld_plane_contexts { 734 uint32_t active_primaries; 735 uint32_t active_sprites; 736 uint32_t active_overlays; 737 struct intel_sprite_context primary_contexts[INTEL_SPRITE_PLANE_NUM]; 738 struct intel_sprite_context sprite_contexts[INTEL_SPRITE_PLANE_NUM]; 739 struct intel_overlay_context overlay_contexts[INTEL_OVERLAY_PLANE_NUM]; 740 }; 741 742 struct drm_psb_vsync_set_arg { 743 uint32_t vsync_operation_mask; 744 745 struct { 746 uint32_t pipe; 747 int vsync_pipe; 748 int vsync_count; 749 uint64_t timestamp; 750 } vsync; 751 }; 752 753 struct drm_psb_dc_info { 754 uint32_t pipe_count; 755 756 uint32_t primary_plane_count; 757 uint32_t sprite_plane_count; 758 uint32_t overlay_plane_count; 759 uint32_t cursor_plane_count; 760 }; 761 762 struct drm_psb_register_rw_arg { 763 uint32_t b_force_hw_on; 764 765 uint32_t display_read_mask; 766 uint32_t display_write_mask; 767 struct { 768 uint32_t pfit_controls; 769 uint32_t pfit_autoscale_ratios; 770 uint32_t pfit_programmed_scale_ratios; 771 uint32_t pipeasrc; 772 uint32_t pipebsrc; 773 uint32_t vtotal_a; 774 uint32_t vtotal_b; 775 uint32_t dspcntr_a; 776 uint32_t dspcntr_b; 777 uint32_t pipestat_a; 778 uint32_t int_mask; 779 uint32_t int_enable; 780 } display; 781 782 uint32_t overlay_read_mask; 783 uint32_t overlay_write_mask; 784 785 struct { 786 uint32_t OVADD; 787 uint32_t OGAMC0; 788 uint32_t OGAMC1; 789 uint32_t OGAMC2; 790 uint32_t OGAMC3; 791 uint32_t OGAMC4; 792 uint32_t OGAMC5; 793 uint32_t IEP_ENABLED; 794 uint32_t IEP_BLE_MINMAX; 795 uint32_t IEP_BSSCC_CONTROL; 796 uint32_t index; 797 uint32_t b_wait_vblank; 798 uint32_t b_wms; 799 uint32_t buffer_handle; 800 } overlay; 801 802 uint32_t vsync_operation_mask; 803 804 struct { 805 uint32_t pipe; 806 int vsync_pipe; 807 int vsync_count; 808 uint64_t timestamp; 809 } vsync; 810 811 uint32_t sprite_enable_mask; 812 uint32_t sprite_disable_mask; 813 814 struct { 815 uint32_t dspa_control; 816 uint32_t dspa_key_value; 817 uint32_t dspa_key_mask; 818 uint32_t dspc_control; 819 uint32_t dspc_stride; 820 uint32_t dspc_position; 821 uint32_t dspc_linear_offset; 822 uint32_t dspc_size; 823 uint32_t dspc_surface; 824 } sprite; 825 826 uint32_t subpicture_enable_mask; 827 uint32_t subpicture_disable_mask; 828 struct { 829 uint32_t CursorADDR; 830 uint32_t xPos; 831 uint32_t yPos; 832 uint32_t CursorSize; 833 } cursor; 834 uint32_t cursor_enable_mask; 835 uint32_t cursor_disable_mask; 836 837 uint32_t plane_enable_mask; 838 uint32_t plane_disable_mask; 839 840 uint32_t get_plane_state_mask; 841 842 struct { 843 uint32_t type; 844 uint32_t index; 845 uint32_t ctx; 846 } plane; 847 }; 848 849 enum { 850 PSB_DC_PLANE_ENABLED, 851 PSB_DC_PLANE_DISABLED, 852 }; 853 854 enum { 855 PSB_GTT_MAP_TYPE_MEMINFO = 0, 856 PSB_GTT_MAP_TYPE_BCD, 857 PSB_GTT_MAP_TYPE_BCD_INFO, 858 PSB_GTT_MAP_TYPE_VIRTUAL, 859 }; 860 861 struct psb_gtt_mapping_arg { 862 uint32_t type; 863 void *hKernelMemInfo; 864 uint32_t offset_pages; 865 uint32_t page_align; 866 uint32_t bcd_device_id; 867 uint32_t bcd_buffer_id; 868 uint32_t bcd_buffer_count; 869 uint32_t bcd_buffer_stride; 870 uint32_t vaddr; 871 uint32_t size; 872 }; 873 874 struct drm_psb_getpageaddrs_arg { 875 uint64_t handle; 876 uint64_t page_addrs; 877 uint64_t gtt_offset; 878 }; 879 880 881 #define MAX_SLICES_PER_PICTURE 72 882 struct psb_msvdx_mb_region { 883 uint32_t start; 884 uint32_t end; 885 }; 886 887 typedef struct drm_psb_msvdx_decode_status { 888 uint32_t num_region; 889 struct psb_msvdx_mb_region mb_regions[MAX_SLICES_PER_PICTURE]; 890 } drm_psb_msvdx_decode_status_t; 891 892 893 enum { 894 IDLE_CTRL_ENABLE = 0, 895 IDLE_CTRL_DISABLE, 896 IDLE_CTRL_ENTER, 897 IDLE_CTRL_EXIT 898 }; 899 900 struct drm_psb_idle_ctrl { 901 uint32_t cmd; 902 uint32_t value; 903 }; 904 905 /* Controlling the kernel modesetting buffers */ 906 907 #define DRM_PSB_KMS_OFF 0x00 908 #define DRM_PSB_KMS_ON 0x01 909 #define DRM_PSB_VT_LEAVE 0x02 910 #define DRM_PSB_VT_ENTER 0x03 911 #define DRM_PSB_EXTENSION 0x06 912 #define DRM_PSB_SIZES 0x07 913 #define DRM_PSB_FUSE_REG 0x08 914 #define DRM_PSB_VBT 0x09 915 #define DRM_PSB_DC_STATE 0x0A 916 #define DRM_PSB_ADB 0x0B 917 #define DRM_PSB_MODE_OPERATION 0x0C 918 #define DRM_PSB_STOLEN_MEMORY 0x0D 919 #define DRM_PSB_REGISTER_RW 0x0E 920 #define DRM_PSB_GTT_MAP 0x0F 921 #define DRM_PSB_GTT_UNMAP 0x10 922 #define DRM_PSB_GETPAGEADDRS 0x11 923 /** 924 * NOTE: Add new commands here, but increment 925 * the values below and increment their 926 * corresponding defines where they're 927 * defined elsewhere. 928 */ 929 #define DRM_PVR_RESERVED1 0x12 930 #define DRM_PVR_RESERVED2 0x13 931 #define DRM_PVR_RESERVED3 0x14 932 #define DRM_PVR_RESERVED4 0x15 933 #define DRM_PVR_RESERVED5 0x16 934 935 #define DRM_PSB_HIST_ENABLE 0x17 936 #define DRM_PSB_HIST_STATUS 0x18 937 #define DRM_PSB_UPDATE_GUARD 0x19 938 #define DRM_PSB_INIT_COMM 0x1A 939 #define DRM_PSB_DPST 0x1B 940 #define DRM_PSB_GAMMA 0x1C 941 #define DRM_PSB_DPST_BL 0x1D 942 943 #define DRM_PVR_RESERVED6 0x1E 944 945 #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F 946 #define DRM_PSB_DPU_QUERY 0x20 947 #define DRM_PSB_DPU_DSR_ON 0x21 948 #define DRM_PSB_DPU_DSR_OFF 0x22 949 #define DRM_PSB_HDMI_FB_CMD 0x23 950 951 /* HDCP IOCTLs */ 952 #define DRM_PSB_QUERY_HDCP 0x24 953 #define DRM_PSB_VALIDATE_HDCP_KSV 0x25 954 #define DRM_PSB_GET_HDCP_STATUS 0x26 955 #define DRM_PSB_ENABLE_HDCP 0x27 956 #define DRM_PSB_DISABLE_HDCP 0x28 957 #define DRM_PSB_GET_HDCP_LINK_STATUS 0x2b 958 #define DRM_PSB_ENABLE_HDCP_REPEATER 0x2c 959 #define DRM_PSB_DISABLE_HDCP_REPEATER 0x2d 960 #define DRM_PSB_HDCP_REPEATER_PRESENT 0x2e 961 962 /* CSC IOCTLS */ 963 #define DRM_PSB_CSC_GAMMA_SETTING 0x29 964 #define DRM_PSB_SET_CSC 0x2a 965 966 /* IED session */ 967 #define DRM_PSB_ENABLE_IED_SESSION 0x30 968 #define DRM_PSB_DISABLE_IED_SESSION 0x31 969 970 /* VSYNC IOCTLS */ 971 #define DRM_PSB_VSYNC_SET 0x32 972 973 /* HDCP */ 974 #define DRM_PSB_HDCP_DISPLAY_IED_OFF 0x33 975 #define DRM_PSB_HDCP_DISPLAY_IED_ON 0x34 976 #define DRM_PSB_QUERY_HDCP_DISPLAY_IED_CAPS 0x35 977 978 /* DPST LEVEL */ 979 #define DRM_PSB_DPST_LEVEL 0x36 980 981 /* GET DC INFO IOCTLS */ 982 #define DRM_PSB_GET_DC_INFO 0x37 983 984 /* Panel type query, 0: command mode, 1: video mode */ 985 #define DRM_PSB_PANEL_QUERY 0x38 986 987 /* IDLE IOCTL*/ 988 #define DRM_PSB_IDLE_CTRL 0x39 989 990 /****BEGIN HDMI TEST IOCTLS ****/ 991 #define DRM_PSB_HDMITEST 0x3A 992 993 /* read an hdmi test register */ 994 #define HT_READ 1 995 /* write an hdmi test register */ 996 #define HT_WRITE 2 997 /* force power island on */ 998 #define HT_FORCEON 4 999 1000 typedef struct tagHDMITESTREGREADWRITE { 1001 /* register offset */ 1002 unsigned int reg; 1003 /* input/output value */ 1004 unsigned int data; 1005 /* OR'ed combo of HT_xx flags */ 1006 int mode; 1007 } drm_psb_hdmireg_t, *drm_psb_hdmireg_p; 1008 1009 /**** END HDMI TEST IOCTLS ****/ 1010 1011 1012 /* GET PANEL ORIENTATION INFO */ 1013 #define DRM_PSB_PANEL_ORIENTATION 0x3B 1014 1015 /* Update cursor position, input is intel_dc_cursor_ctx */ 1016 #define DRM_PSB_UPDATE_CURSOR_POS 0x3C 1017 1018 1019 /* Do not use IOCTL between 0x40 and 0x4F */ 1020 /* These will be reserved for OEM to use */ 1021 /* OEM IOCTLs */ 1022 #define DRM_OEM_RESERVED_START 0x40 1023 #define DRM_OEM_RESERVED_END 0x4F 1024 1025 1026 /* 1027 * TTM execbuf extension. 1028 */ 1029 #define DRM_PSB_TTM_START 0x50 1030 #define DRM_PSB_TTM_END 0x5F 1031 #if defined(PDUMP) 1032 #define DRM_PSB_CMDBUF (PVR_DRM_DBGDRV_CMD + 1) 1033 #else 1034 #define DRM_PSB_CMDBUF (DRM_PSB_TTM_START) 1035 #endif 1036 #define DRM_PSB_SCENE_UNREF (DRM_PSB_CMDBUF + 1) 1037 #define DRM_PSB_PLACEMENT_OFFSET (DRM_PSB_SCENE_UNREF + 1) 1038 1039 1040 1041 1042 #define DRM_PSB_DSR_ENABLE 0xfffffffe 1043 #define DRM_PSB_DSR_DISABLE 0xffffffff 1044 1045 struct drm_psb_csc_matrix { 1046 int pipe; 1047 int64_t matrix[9]; 1048 }__attribute__((packed)); 1049 1050 struct psb_drm_dpu_rect { 1051 int x, y; 1052 int width, height; 1053 }; 1054 1055 struct drm_psb_drv_dsr_off_arg { 1056 int screen; 1057 struct psb_drm_dpu_rect damage_rect; 1058 }; 1059 1060 1061 struct drm_psb_dev_info_arg { 1062 uint32_t num_use_attribute_registers; 1063 }; 1064 #define DRM_PSB_DEVINFO 0x01 1065 #define PSB_MODE_OPERATION_MODE_VALID 0x01 1066 #define PSB_MODE_OPERATION_SET_DC_BASE 0x02 1067 1068 struct drm_psb_get_pipe_from_crtc_id_arg { 1069 /** ID of CRTC being requested **/ 1070 uint32_t crtc_id; 1071 1072 /** pipe of requested CRTC **/ 1073 uint32_t pipe; 1074 }; 1075 #define DRM_PSB_DISP_SAVE_HDMI_FB_HANDLE 1 1076 #define DRM_PSB_DISP_GET_HDMI_FB_HANDLE 2 1077 #define DRM_PSB_DISP_INIT_HDMI_FLIP_CHAIN 1 1078 #define DRM_PSB_DISP_QUEUE_BUFFER 2 1079 #define DRM_PSB_DISP_DEQUEUE_BUFFER 3 1080 #define DRM_PSB_DISP_PLANEB_DISABLE 4 1081 #define DRM_PSB_DISP_PLANEB_ENABLE 5 1082 #define DRM_PSB_HDMI_OSPM_ISLAND_DOWN 6 1083 #define DRM_PSB_HDMI_NOTIFY_HOTPLUG_TO_AUDIO 7 1084 1085 /*csc gamma setting*/ 1086 typedef enum { 1087 GAMMA, 1088 CSC, 1089 GAMMA_INITIA, 1090 GAMMA_SETTING, 1091 GAMMA_REG_SETTING, 1092 CSC_INITIA, 1093 CSC_CHROME_SETTING, 1094 CSC_SETTING, 1095 CSC_REG_SETTING 1096 } setting_type; 1097 1098 typedef enum { 1099 /* gamma 0.5 */ 1100 GAMMA_05 = 1, 1101 /* gamma 2.0 */ 1102 GAMMA_20, 1103 /* gamma 0.5 + 2.0*/ 1104 GAMMA_05_20, 1105 /* gamma 2.0 + 0.5*/ 1106 GAMMA_20_05, 1107 /* gamma 1.0 */ 1108 GAMMA_10 1109 } gamma_mode; 1110 1111 #define CSC_REG_COUNT 6 1112 #define CHROME_COUNT 16 1113 #define CSC_COUNT 9 1114 1115 struct csc_setting { 1116 uint32_t pipe; 1117 setting_type type; 1118 bool enable_state; 1119 uint32_t data_len; 1120 union { 1121 int csc_reg_data[CSC_REG_COUNT]; 1122 int chrome_data[CHROME_COUNT]; 1123 int64_t csc_data[CSC_COUNT]; 1124 } data; 1125 }; 1126 #define GAMMA_10_BIT_TABLE_COUNT 129 1127 1128 struct gamma_setting { 1129 uint32_t pipe; 1130 setting_type type; 1131 bool enable_state; 1132 gamma_mode initia_mode; 1133 uint32_t data_len; 1134 uint32_t gamma_tableX100[GAMMA_10_BIT_TABLE_COUNT]; 1135 }; 1136 struct drm_psb_csc_gamma_setting { 1137 setting_type type; 1138 union { 1139 struct csc_setting csc_data; 1140 struct gamma_setting gamma_data; 1141 } data; 1142 }__attribute__((packed)); 1143 struct drm_psb_buffer_data { 1144 void *h_buffer; 1145 }; 1146 struct drm_psb_flip_chain_data { 1147 void **h_buffer_array; 1148 unsigned int size; 1149 }; 1150 struct drm_psb_disp_ctrl { 1151 uint32_t cmd; 1152 union { 1153 uint32_t data; 1154 struct drm_psb_buffer_data buf_data; 1155 struct drm_psb_flip_chain_data flip_chain_data; 1156 } u; 1157 }; 1158 1159 /* Merrifield driver specific interface */ 1160 1161 #define S3D_MIPIA_DISPLAY 0 1162 #define S3D_HDMI_DISPLAY 1 1163 #define S3D_MIPIC_DISPLAY 2 1164 #define S3D_WIDI_DISPLAY 0xFF 1165 1166 struct drm_psb_s3d_query { 1167 uint32_t s3d_display_type; 1168 uint32_t is_s3d_supported; 1169 uint32_t s3d_format; 1170 uint32_t mode_resolution_x; 1171 uint32_t mode_resolution_y; 1172 uint32_t mode_refresh_rate; 1173 uint32_t is_interleaving; 1174 }; 1175 1176 struct drm_psb_s3d_premodeset { 1177 uint32_t s3d_buffer_format; 1178 }; 1179 1180 1181 typedef enum intel_dc_plane_types { 1182 DC_UNKNOWN_PLANE = 0, 1183 DC_SPRITE_PLANE = 1, 1184 DC_OVERLAY_PLANE, 1185 DC_PRIMARY_PLANE, 1186 DC_CURSOR_PLANE, 1187 DC_PLANE_MAX, 1188 } DC_MRFLD_PLANE_TYPE; 1189 1190 #define SPRITE_UPDATE_SURFACE (0x00000001UL) 1191 #define SPRITE_UPDATE_CONTROL (0x00000002UL) 1192 #define SPRITE_UPDATE_POSITION (0x00000004UL) 1193 #define SPRITE_UPDATE_SIZE (0x00000008UL) 1194 #define SPRITE_UPDATE_WAIT_VBLANK (0X00000010UL) 1195 #define SPRITE_UPDATE_CONSTALPHA (0x00000020UL) 1196 #define SPRITE_UPDATE_ALL (0x0000003fUL) 1197 #define MRFLD_PRIMARY_COUNT 3 1198 1199 typedef struct intel_dc_overlay_ctx { 1200 uint32_t index; 1201 uint32_t pipe; 1202 uint32_t ovadd; 1203 } DC_MRFLD_OVERLAY_CONTEXT; 1204 1205 typedef struct intel_dc_cursor_ctx { 1206 uint32_t index; 1207 uint32_t pipe; 1208 uint32_t cntr; 1209 uint32_t surf; 1210 uint32_t pos; 1211 } DC_MRFLD_CURSOR_CONTEXT; 1212 1213 typedef struct intel_dc_sprite_ctx { 1214 uint32_t update_mask; 1215 /* plane index 0-A, 1-B, 2-C,etc */ 1216 uint32_t index; 1217 uint32_t pipe; 1218 1219 uint32_t cntr; 1220 uint32_t linoff; 1221 uint32_t stride; 1222 uint32_t pos; 1223 uint32_t size; 1224 uint32_t keyminval; 1225 uint32_t keymask; 1226 uint32_t surf; 1227 uint32_t keymaxval; 1228 uint32_t tileoff; 1229 uint32_t contalpa; 1230 } DC_MRFLD_SPRITE_CONTEXT; 1231 1232 typedef struct intel_dc_primary_ctx { 1233 uint32_t update_mask; 1234 /* plane index 0-A, 1-B, 2-C,etc */ 1235 uint32_t index; 1236 uint32_t pipe; 1237 uint32_t cntr; 1238 uint32_t linoff; 1239 uint32_t stride; 1240 uint32_t pos; 1241 uint32_t size; 1242 uint32_t keyminval; 1243 uint32_t keymask; 1244 uint32_t surf; 1245 uint32_t keymaxval; 1246 uint32_t tileoff; 1247 uint32_t contalpa; 1248 } DC_MRFLD_PRIMARY_CONTEXT; 1249 1250 typedef struct intel_dc_plane_zorder { 1251 /* 3 primary planes */ 1252 uint32_t forceBottom[3]; 1253 /* 1 sprite plane */ 1254 uint32_t abovePrimary; 1255 } DC_MRFLD_DC_PLANE_ZORDER; 1256 1257 typedef struct intel_dc_plane_ctx { 1258 enum intel_dc_plane_types type; 1259 struct intel_dc_plane_zorder zorder; 1260 union { 1261 struct intel_dc_overlay_ctx ov_ctx; 1262 struct intel_dc_sprite_ctx sp_ctx; 1263 struct intel_dc_primary_ctx prim_ctx; 1264 struct intel_dc_cursor_ctx cs_ctx; 1265 } ctx; 1266 } DC_MRFLD_SURF_CUSTOM; 1267 1268 #endif 1269
