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      1 #BCM4358 WLBGA module for iPA, eLNA board with PCIE for production package
      2 #adding two range TSSI parameters
      3 NVRAMRev=$Rev: 500210 $
      4 sromrev=11
      5 boardrev=0x1100
      6 ## boardtype is subject to change
      7 boardtype=0x07a1
      8 boardflags=0x12001001
      9 #enable eLNA both 2G/5G
     10 boardflags2=0x00002000
     11 boardflags3=0x48000109
     12 #boardnum=57410
     13 macaddr=00:90:4c:16:70:01
     14 ccode=ALL
     15 regrev=0
     16 antswitch=0
     17 pdgain5g=4
     18 pdgain2g=4
     19 tworangetssi2g=0
     20 tworangetssi5g=0
     21 lowpowerrange2g=0
     22 lowpowerrange5g=0
     23 olpc_thresh=1
     24 femctrl=10
     25 vendid=0x14e4
     26 devid=0x43e9
     27 manfid=0x2d0
     28 #prodid=0x052e
     29 nocrc=1
     30 otpimagesize=484
     31 xtalfreq=37400
     32 ltecxmux=0x78560
     33 
     34 rxgains2gelnagaina0=3
     35 rxgains2gtrisoa0=8
     36 rxgains2gtrelnabypa0=1
     37 rxgains5gelnagaina0=3
     38 rxgains5gtrisoa0=7
     39 rxgains5gtrelnabypa0=1
     40 rxgains5gmelnagaina0=3
     41 rxgains5gmtrisoa0=7
     42 rxgains5gmtrelnabypa0=1
     43 rxgains5ghelnagaina0=3
     44 rxgains5ghtrisoa0=6
     45 rxgains5ghtrelnabypa0=1
     46 rxgains2gelnagaina1=3
     47 rxgains2gtrisoa1=8
     48 rxgains2gtrelnabypa1=1
     49 rxgains5gelnagaina1=3
     50 rxgains5gtrisoa1=7
     51 rxgains5gtrelnabypa1=1
     52 rxgains5gmelnagaina1=3
     53 rxgains5gmtrisoa1=7
     54 rxgains5gmtrelnabypa1=1
     55 rxgains5ghelnagaina1=3
     56 rxgains5ghtrisoa1=6
     57 rxgains5ghtrelnabypa1=1
     58 rxchain=3
     59 txchain=3
     60 aa2g=3
     61 aa5g=3
     62 agbg0=0
     63 agbg1=0
     64 aga0=0
     65 aga1=0
     66 tssipos2g=1
     67 extpagain2g=2
     68 tssipos5g=1
     69 extpagain5g=2
     70 tempthresh=120
     71 temps_hysteresis=15
     72 tempoffset=255
     73 rawtempsense=0x1ff
     74 
     75 #PA parameters copied from 4356 wlbga design bcm94356wlsagbl
     76 
     77 pa2gccka0=0xff34,0x1557,0xfd57
     78 pa2ga0=0xff44,0x15de,0xfd58
     79 #pa5ga0=-166,6427,-744,-174,6340,-742,-188,6004,-721,-178,6037,-714
     80 pa5ga0=0xff3a,0x16fc,0xfd30,0xff37,0x16fe,0xfd2e,0xff40,0x16d3,0xfd3a,0xff3a,0x1643,0xfd46
     81 
     82 pa2gccka1=0xff47,0x176a,0xfd21
     83 pa2ga1=0xff4b,0x16bb,0xfd41
     84 #pa5ga1=-168,6277,-731,-189,5964,-722,-173,6056,-712,-165,6195,-718
     85 pa5ga1=0xff3c,0x17ea,0xfd18,0xff3c,0x17af,0xfd1c,0xff43,0x16f5,0xfd36,0xff40,0x16ff,0xfd34
     86 
     87 
     88 #pa2ga0=-165,5774,-687
     89 #pa2ga1=-151,6040,-693
     90 #pa5ga0=-171,5985,-715,-164,5988,-710,-149,5992,-688,-165,5935,-699
     91 #pa5ga1=-178,6049,-724,-166,6117,-721,-157,6073,-704,-164,6043,-712
     92 
     93 ###low range
     94 #pa2ga2=-108,4009,-577
     95 #pa2ga3=-129,4081,-572
     96 #pa5ga2=-101,4150,-583,-103,4080,-582,-80,4147,-590,-120,3997,-567
     97 #pa5ga3=-139,4129,-579,-133,4111,-580,-115,4129,-581,-121,4120,-577
     98 
     99 maxp2ga0=82
    100 maxp5ga0=82,82,82,82
    101 maxp2ga1=82
    102 maxp5ga1=82,82,82,82
    103 
    104 
    105 subband5gver=0x4
    106 pdoffsetcckma0=0x2
    107 pdoffsetcckma1=0x2
    108 pdoffset40ma0=0x2222
    109 pdoffset80ma0=0x0000
    110 pdoffset40ma1=0x2222
    111 pdoffset80ma1=0x0000
    112 cckbw202gpo=0x2222
    113 cckbw20ul2gpo=0x2222
    114 
    115 mcsbw202gpo=0xDC655442
    116 mcsbw402gpo=0xFE777666
    117 dot11agofdmhrbw202gpo=0x4431
    118 ofdmlrbw202gpo=0x1111
    119 
    120 mcsbw205glpo=0xA9654431
    121 mcsbw405glpo=0xA9864444
    122 mcsbw805glpo=0xcc865555
    123 #mcsbw805glpo=0xBB865555
    124 
    125 mcsbw205gmpo=0xA9654431
    126 mcsbw405gmpo=0xA9864444
    127 mcsbw805gmpo=0xcc865555
    128 
    129 mcsbw205ghpo=0x99654431
    130 mcsbw405ghpo=0xA9864444
    131 mcsbw805ghpo=0xfe865555
    132 
    133 mcslr5glpo=0x0000
    134 mcslr5gmpo=0x0000
    135 mcslr5ghpo=0x0000
    136 
    137 sb20in40hrpo=0x0
    138 sb20in80and160hr5glpo=0x0
    139 sb40and80hr5glpo=0x0
    140 sb20in80and160hr5gmpo=0x0
    141 sb40and80hr5gmpo=0x0
    142 sb20in80and160hr5ghpo=0x0
    143 sb40and80hr5ghpo=0x0
    144 sb20in40lrpo=0x0
    145 sb20in80and160lr5glpo=0x0
    146 sb40and80lr5glpo=0x0
    147 sb20in80and160lr5gmpo=0x0
    148 sb40and80lr5gmpo=0x0
    149 sb20in80and160lr5ghpo=0x0
    150 sb40and80lr5ghpo=0x0
    151 dot11agduphrpo=0x0
    152 dot11agduplrpo=0x0
    153 phycal_tempdelta=25
    154 temps_period=15
    155 phy4350_ss_opt=1
    156 AvVmid_c0=2,140,2,145,2,145,2,145,2,145
    157 AvVmid_c1=2,140,2,145,2,145,2,145,2,145
    158 rssicorrnorm_c0=-1,-1
    159 rssicorrnorm_c1=-1,-1
    160 rssicorrnorm5g_c0=1,2,2,0,2,2,1,2,2,1,2,3
    161 rssicorrnorm5g_c1=0,1,2,0,1,2,0,1,2,0,1,2
    162 epsdelta2g0=0
    163 epsdelta2g1=0
    164 papdwar=4
    165 cckdigfilttype=2
    166 cck_onecore_tx=1
    167 tssisleep_en=0x1f
    168 
    169 swctrlmap_5g=0x02080208,0x05a00000,0x04200000,0x000000,0x0fd
    170 swctrlmap_2g=0x14011401,0x28500000,0x08100000,0x020202,0x0ff
    171 #fem_table_init_val=0x1,0x1
    172 swctrlmapext_2g=0x0,0x0,0x0,0x0,0x03
    173 
    174 ## Enabling OOB signal - needed for final board
    175 host_wake_opt=0
    176 
    177 # For Sensor Hub UART
    178 #muxenab=0x4
    179 
    180 ## 2G TX power compensation
    181 #powoffs2gtna0=0,-1,-1,0,2,3,4,4,2,0,-1,-2,-1,0
    182 powoffs2gtna0=0,0,0,0,0,-1,-1,0,0,0,0,1,1,0
    183 powoffs2gtna1=0,0,0,0,0,-1,-1,0,0,0,1,1,1,0
    184 
    185 #rpcal2g=10
    186 #rpcal5gb0=20
    187 #rpcal5gb1=10
    188 #rpcal5gb2=20
    189 #rpcal5gb3=10
    190 
    191 #dynamicsarctrl_2g=0xffb0
    192 #dynamicsarctrl_5g=0xffa0
    193 
    194 ofdmfilttype=1
    195 ofdmfiltbesel_2g=0x39
    196 ofdmfiltbe_2g=4
    197 ofdmfiltbesel_5g20=0x3f
    198 ofdmfiltbe_5g20=4
    199 ofdmfiltbesel_5g40=0x1f
    200 ofdmfiltbe_5g40=4
    201 ofdmfiltbesel_5g80=0xf
    202 ofdmfiltbe_5g80=4
    203 
    204 btc_params82=0x0
    205 btc_params51=0x409f
    206 btc_params73=0
    207 prot_btrssi_thresh=0
    208 
    209 pacalshift5ga0=0,0,0,0,-2,-2,0,-2,0,-2,0,-3
    210 pacalshift5ga1=0,0,0,0,-2,-1,0,-2,-2,-2,0,-3
    211 
    212 # ###########  BTC Dynctl profile params  ############
    213 # flags:bit0 - dynctl enabled, bit1 dynamic desense, bit2 dynamic mode
    214 btcdyn_flags=0x7
    215 btcdyn_dflt_dsns_level=0
    216 btcdyn_low_dsns_level=0
    217 btcdyn_mid_dsns_level=12
    218 btcdyn_high_dsns_level=2
    219 btcdyn_default_btc_mode=1
    220 # --- number of rows in the array vars below ---
    221 btcdyn_msw_rows=1
    222 btcdyn_dsns_rows=1
    223 # --- mode switch data rows (max is 4) ---
    224 btcdyn_msw_row0=1,12,-70,-5,-100
    225 # --- desense switching data rows (max is 4) ---
    226 btcdyn_dsns_row0=5,4,0,-65,-65
    227 ## btc parameters should be added
    228