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      1 /*
      2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions are met:
      6  *
      7  * Redistributions of source code must retain the above copyright notice, this
      8  * list of conditions and the following disclaimer.
      9  *
     10  * Redistributions in binary form must reproduce the above copyright notice,
     11  * this list of conditions and the following disclaimer in the documentation
     12  * and/or other materials provided with the distribution.
     13  *
     14  * Neither the name of ARM nor the names of its contributors may be used
     15  * to endorse or promote products derived from this software without specific
     16  * prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #include <arch.h>
     32 #include <asm_macros.S>
     33 #include <bl_common.h>
     34 
     35 
     36 	.globl	bl2_entrypoint
     37 
     38 
     39 
     40 func bl2_entrypoint
     41 	/*---------------------------------------------
     42 	 * Store the extents of the tzram available to
     43 	 * BL2 for future use. Use the opcode param to
     44 	 * allow implement other functions if needed.
     45 	 * ---------------------------------------------
     46 	 */
     47 	mov	x20, x0
     48 	mov	x21, x1
     49 
     50 	/* ---------------------------------------------
     51 	 * Set the exception vector to something sane.
     52 	 * ---------------------------------------------
     53 	 */
     54 	adr	x0, early_exceptions
     55 	msr	vbar_el1, x0
     56 	isb
     57 
     58 	/* ---------------------------------------------
     59 	 * Enable the SError interrupt now that the
     60 	 * exception vectors have been setup.
     61 	 * ---------------------------------------------
     62 	 */
     63 	msr	daifclr, #DAIF_ABT_BIT
     64 
     65 	/* ---------------------------------------------
     66 	 * Enable the instruction cache, stack pointer
     67 	 * and data access alignment checks
     68 	 * ---------------------------------------------
     69 	 */
     70 	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
     71 	mrs	x0, sctlr_el1
     72 	orr	x0, x0, x1
     73 	msr	sctlr_el1, x0
     74 	isb
     75 
     76 	/* ---------------------------------------------
     77 	 * Check the opcodes out of paranoia.
     78 	 * ---------------------------------------------
     79 	 */
     80 	mov	x0, #RUN_IMAGE
     81 	cmp	x0, x20
     82 	b.ne	_panic
     83 
     84 	/* ---------------------------------------------
     85 	 * Zero out NOBITS sections. There are 2 of them:
     86 	 *   - the .bss section;
     87 	 *   - the coherent memory section.
     88 	 * ---------------------------------------------
     89 	 */
     90 	ldr	x0, =__BSS_START__
     91 	ldr	x1, =__BSS_SIZE__
     92 	bl	zeromem16
     93 
     94 #if USE_COHERENT_MEM
     95 	ldr	x0, =__COHERENT_RAM_START__
     96 	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
     97 	bl	zeromem16
     98 #endif
     99 
    100 	/* --------------------------------------------
    101 	 * Allocate a stack whose memory will be marked
    102 	 * as Normal-IS-WBWA when the MMU is enabled.
    103 	 * There is no risk of reading stale stack
    104 	 * memory after enabling the MMU as only the
    105 	 * primary cpu is running at the moment.
    106 	 * --------------------------------------------
    107 	 */
    108 	mrs	x0, mpidr_el1
    109 	bl	platform_set_stack
    110 
    111 	/* ---------------------------------------------
    112 	 * Perform early platform setup & platform
    113 	 * specific early arch. setup e.g. mmu setup
    114 	 * ---------------------------------------------
    115 	 */
    116 	mov	x0, x21
    117 	bl	bl2_early_platform_setup
    118 	bl	bl2_plat_arch_setup
    119 
    120 	/* ---------------------------------------------
    121 	 * Jump to main function.
    122 	 * ---------------------------------------------
    123 	 */
    124 	bl	bl2_main
    125 _panic:
    126 	b	_panic
    127