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      1 /*
      2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions are met:
      6  *
      7  * Redistributions of source code must retain the above copyright notice, this
      8  * list of conditions and the following disclaimer.
      9  *
     10  * Redistributions in binary form must reproduce the above copyright notice,
     11  * this list of conditions and the following disclaimer in the documentation
     12  * and/or other materials provided with the distribution.
     13  *
     14  * Neither the name of ARM nor the names of its contributors may be used
     15  * to endorse or promote products derived from this software without specific
     16  * prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #include <platform_def.h>
     32 
     33 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
     34 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
     35 ENTRY(bl2_entrypoint)
     36 
     37 MEMORY {
     38     RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
     39 }
     40 
     41 
     42 SECTIONS
     43 {
     44     . = BL2_BASE;
     45     ASSERT(. == ALIGN(4096),
     46            "BL2_BASE address is not aligned on a page boundary.")
     47 
     48     ro . : {
     49         __RO_START__ = .;
     50         *bl2_entrypoint.o(.text*)
     51         *(.text*)
     52         *(.rodata*)
     53         *(.vectors)
     54         __RO_END_UNALIGNED__ = .;
     55         /*
     56          * Memory page(s) mapped to this section will be marked as
     57          * read-only, executable.  No RW data from the next section must
     58          * creep in.  Ensure the rest of the current memory page is unused.
     59          */
     60         . = NEXT(4096);
     61         __RO_END__ = .;
     62     } >RAM
     63 
     64     .data . : {
     65         __DATA_START__ = .;
     66         *(.data*)
     67         __DATA_END__ = .;
     68     } >RAM
     69 
     70     stacks (NOLOAD) : {
     71         __STACKS_START__ = .;
     72         *(tzfw_normal_stacks)
     73         __STACKS_END__ = .;
     74     } >RAM
     75 
     76     /*
     77      * The .bss section gets initialised to 0 at runtime.
     78      * Its base address must be 16-byte aligned.
     79      */
     80     .bss : ALIGN(16) {
     81         __BSS_START__ = .;
     82         *(SORT_BY_ALIGNMENT(.bss*))
     83         *(COMMON)
     84         __BSS_END__ = .;
     85     } >RAM
     86 
     87     /*
     88      * The xlat_table section is for full, aligned page tables (4K).
     89      * Removing them from .bss avoids forcing 4K alignment on
     90      * the .bss section and eliminates the unecessary zero init
     91      */
     92     xlat_table (NOLOAD) : {
     93         *(xlat_table)
     94     } >RAM
     95 
     96 #if USE_COHERENT_MEM
     97     /*
     98      * The base address of the coherent memory section must be page-aligned (4K)
     99      * to guarantee that the coherent data are stored on their own pages and
    100      * are not mixed with normal data.  This is required to set up the correct
    101      * memory attributes for the coherent data page tables.
    102      */
    103     coherent_ram (NOLOAD) : ALIGN(4096) {
    104         __COHERENT_RAM_START__ = .;
    105         *(tzfw_coherent_mem)
    106         __COHERENT_RAM_END_UNALIGNED__ = .;
    107         /*
    108          * Memory page(s) mapped to this section will be marked
    109          * as device memory.  No other unexpected data must creep in.
    110          * Ensure the rest of the current memory page is unused.
    111          */
    112         . = NEXT(4096);
    113         __COHERENT_RAM_END__ = .;
    114     } >RAM
    115 #endif
    116 
    117     __BL2_END__ = .;
    118 
    119     __BSS_SIZE__ = SIZEOF(.bss);
    120 
    121 #if USE_COHERENT_MEM
    122     __COHERENT_RAM_UNALIGNED_SIZE__ =
    123         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
    124 #endif
    125 
    126     ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
    127 }
    128