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      1 /*
      2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions are met:
      6  *
      7  * Redistributions of source code must retain the above copyright notice, this
      8  * list of conditions and the following disclaimer.
      9  *
     10  * Redistributions in binary form must reproduce the above copyright notice,
     11  * this list of conditions and the following disclaimer in the documentation
     12  * and/or other materials provided with the distribution.
     13  *
     14  * Neither the name of ARM nor the names of its contributors may be used
     15  * to endorse or promote products derived from this software without specific
     16  * prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #include <platform_def.h>
     32 
     33 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
     34 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
     35 ENTRY(bl31_entrypoint)
     36 
     37 
     38 MEMORY {
     39     RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
     40 }
     41 
     42 
     43 SECTIONS
     44 {
     45     . = BL31_BASE;
     46     ASSERT(. == ALIGN(4096),
     47            "BL31_BASE address is not aligned on a page boundary.")
     48 
     49     ro . : {
     50         __RO_START__ = .;
     51         *bl31_entrypoint.o(.text*)
     52         *(.text*)
     53         *(.rodata*)
     54 
     55         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
     56         . = ALIGN(8);
     57         __RT_SVC_DESCS_START__ = .;
     58         KEEP(*(rt_svc_descs))
     59         __RT_SVC_DESCS_END__ = .;
     60 
     61         /*
     62          * Ensure 8-byte alignment for cpu_ops so that its fields are also
     63          * aligned. Also ensure cpu_ops inclusion.
     64          */
     65         . = ALIGN(8);
     66         __CPU_OPS_START__ = .;
     67         KEEP(*(cpu_ops))
     68         __CPU_OPS_END__ = .;
     69 
     70         *(.vectors)
     71         __RO_END_UNALIGNED__ = .;
     72         /*
     73          * Memory page(s) mapped to this section will be marked as read-only,
     74          * executable.  No RW data from the next section must creep in.
     75          * Ensure the rest of the current memory page is unused.
     76          */
     77         . = NEXT(4096);
     78         __RO_END__ = .;
     79     } >RAM
     80 
     81     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
     82            "cpu_ops not defined for this platform.")
     83 
     84     .data . : {
     85         __DATA_START__ = .;
     86         *(.data*)
     87         __DATA_END__ = .;
     88     } >RAM
     89 
     90 #ifdef BL31_PROGBITS_LIMIT
     91     ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.")
     92 #endif
     93 
     94     stacks (NOLOAD) : {
     95         __STACKS_START__ = .;
     96         *(tzfw_normal_stacks)
     97         __STACKS_END__ = .;
     98     } >RAM
     99 
    100     /*
    101      * The .bss section gets initialised to 0 at runtime.
    102      * Its base address must be 16-byte aligned.
    103      */
    104     .bss : ALIGN(16) {
    105         __BSS_START__ = .;
    106         *(.bss*)
    107         *(COMMON)
    108         __BSS_END__ = .;
    109     } >RAM
    110 
    111     /*
    112      * The xlat_table section is for full, aligned page tables (4K).
    113      * Removing them from .bss avoids forcing 4K alignment on
    114      * the .bss section and eliminates the unecessary zero init
    115      */
    116     xlat_table (NOLOAD) : {
    117         *(xlat_table)
    118     } >RAM
    119 
    120 #if USE_COHERENT_MEM
    121     /*
    122      * The base address of the coherent memory section must be page-aligned (4K)
    123      * to guarantee that the coherent data are stored on their own pages and
    124      * are not mixed with normal data.  This is required to set up the correct
    125      * memory attributes for the coherent data page tables.
    126      */
    127     coherent_ram (NOLOAD) : ALIGN(4096) {
    128         __COHERENT_RAM_START__ = .;
    129         *(tzfw_coherent_mem)
    130         __COHERENT_RAM_END_UNALIGNED__ = .;
    131         /*
    132          * Memory page(s) mapped to this section will be marked
    133          * as device memory.  No other unexpected data must creep in.
    134          * Ensure the rest of the current memory page is unused.
    135          */
    136         . = NEXT(4096);
    137         __COHERENT_RAM_END__ = .;
    138     } >RAM
    139 #endif
    140 
    141     __BL31_END__ = .;
    142 
    143     __BSS_SIZE__ = SIZEOF(.bss);
    144 #if USE_COHERENT_MEM
    145     __COHERENT_RAM_UNALIGNED_SIZE__ =
    146         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
    147 #endif
    148 
    149     ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
    150 }
    151