1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <gic_v2.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <tsp.h> 38 #include "tsp_private.h" 39 40 /******************************************************************************* 41 * This function updates the TSP statistics for FIQs handled synchronously i.e 42 * the ones that have been handed over by the TSPD. It also keeps count of the 43 * number of times control was passed back to the TSPD after handling an FIQ. 44 * In the future it will be possible that the TSPD hands over an FIQ to the TSP 45 * but does not expect it to return execution. This statistic will be useful to 46 * distinguish between these two models of synchronous FIQ handling. 47 * The 'elr_el3' parameter contains the address of the instruction in normal 48 * world where this FIQ was generated. 49 ******************************************************************************/ 50 void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) 51 { 52 uint64_t mpidr = read_mpidr(); 53 uint32_t linear_id = platform_get_core_pos(mpidr); 54 55 tsp_stats[linear_id].sync_fiq_count++; 56 if (type == TSP_HANDLE_FIQ_AND_RETURN) 57 tsp_stats[linear_id].sync_fiq_ret_count++; 58 59 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 60 spin_lock(&console_lock); 61 VERBOSE("TSP: cpu 0x%x sync fiq request from 0x%llx\n", 62 mpidr, elr_el3); 63 VERBOSE("TSP: cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n", 64 mpidr, 65 tsp_stats[linear_id].sync_fiq_count, 66 tsp_stats[linear_id].sync_fiq_ret_count); 67 spin_unlock(&console_lock); 68 #endif 69 } 70 71 /******************************************************************************* 72 * TSP FIQ handler called as a part of both synchronous and asynchronous 73 * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 74 * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC 75 * architecture version in v2.0 and the secure physical timer interrupt is the 76 * only S-EL1 interrupt that it needs to handle. 77 ******************************************************************************/ 78 int32_t tsp_fiq_handler(void) 79 { 80 uint64_t mpidr = read_mpidr(); 81 uint32_t linear_id = platform_get_core_pos(mpidr), id; 82 83 /* 84 * Get the highest priority pending interrupt id and see if it is the 85 * secure physical generic timer interrupt in which case, handle it. 86 * Otherwise throw this interrupt at the EL3 firmware. 87 */ 88 id = plat_ic_get_pending_interrupt_id(); 89 90 /* TSP can only handle the secure physical timer interrupt */ 91 if (id != TSP_IRQ_SEC_PHY_TIMER) 92 return TSP_EL3_FIQ; 93 94 /* 95 * Handle the interrupt. Also sanity check if it has been preempted by 96 * another secure interrupt through an assertion. 97 */ 98 id = plat_ic_acknowledge_interrupt(); 99 assert(id == TSP_IRQ_SEC_PHY_TIMER); 100 tsp_generic_timer_handler(); 101 plat_ic_end_of_interrupt(id); 102 103 /* Update the statistics and print some messages */ 104 tsp_stats[linear_id].fiq_count++; 105 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 106 spin_lock(&console_lock); 107 VERBOSE("TSP: cpu 0x%x handled fiq %d\n", 108 mpidr, id); 109 VERBOSE("TSP: cpu 0x%x: %d fiq requests\n", 110 mpidr, tsp_stats[linear_id].fiq_count); 111 spin_unlock(&console_lock); 112 #endif 113 return 0; 114 } 115 116 int32_t tsp_irq_received(void) 117 { 118 uint64_t mpidr = read_mpidr(); 119 uint32_t linear_id = platform_get_core_pos(mpidr); 120 121 tsp_stats[linear_id].irq_count++; 122 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 123 spin_lock(&console_lock); 124 VERBOSE("TSP: cpu 0x%x received irq\n", mpidr); 125 VERBOSE("TSP: cpu 0x%x: %d irq requests\n", 126 mpidr, tsp_stats[linear_id].irq_count); 127 spin_unlock(&console_lock); 128 #endif 129 return TSP_PREEMPTED; 130 } 131
