1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /dts-v1/; 32 33 /memreserve/ 0x80000000 0x00010000; 34 35 / { 36 }; 37 38 / { 39 model = "FVP Base"; 40 compatible = "arm,vfp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { }; 46 47 aliases { 48 serial0 = &v2m_serial0; 49 serial1 = &v2m_serial1; 50 serial2 = &v2m_serial2; 51 serial3 = &v2m_serial3; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 56 method = "smc"; 57 cpu_suspend = <0xc4000001>; 58 cpu_off = <0x84000002>; 59 cpu_on = <0xc4000003>; 60 sys_poweroff = <0x84000008>; 61 sys_reset = <0x84000009>; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 }; 83 84 cluster1 { 85 core0 { 86 cpu = <&CPU4>; 87 }; 88 core1 { 89 cpu = <&CPU5>; 90 }; 91 core2 { 92 cpu = <&CPU6>; 93 }; 94 core3 { 95 cpu = <&CPU7>; 96 }; 97 }; 98 }; 99 100 idle-states { 101 entry-method = "arm,psci"; 102 103 CPU_SLEEP_0: cpu-sleep-0 { 104 compatible = "arm,idle-state"; 105 entry-method-param = <0x0010000>; 106 entry-latency-us = <40>; 107 exit-latency-us = <100>; 108 min-residency-us = <150>; 109 }; 110 111 CLUSTER_SLEEP_0: cluster-sleep-0 { 112 compatible = "arm,idle-state"; 113 entry-method-param = <0x1010000>; 114 entry-latency-us = <500>; 115 exit-latency-us = <1000>; 116 min-residency-us = <2500>; 117 }; 118 }; 119 120 CPU0:cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,armv8"; 123 reg = <0x0 0x0>; 124 enable-method = "psci"; 125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 126 }; 127 128 CPU1:cpu@1 { 129 device_type = "cpu"; 130 compatible = "arm,armv8"; 131 reg = <0x0 0x1>; 132 enable-method = "psci"; 133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 134 }; 135 136 CPU2:cpu@2 { 137 device_type = "cpu"; 138 compatible = "arm,armv8"; 139 reg = <0x0 0x2>; 140 enable-method = "psci"; 141 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 142 }; 143 144 CPU3:cpu@3 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0 0x3>; 148 enable-method = "psci"; 149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 150 }; 151 152 CPU4:cpu@100 { 153 device_type = "cpu"; 154 compatible = "arm,armv8"; 155 reg = <0x0 0x100>; 156 enable-method = "psci"; 157 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 158 }; 159 160 CPU5:cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,armv8"; 163 reg = <0x0 0x101>; 164 enable-method = "psci"; 165 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 166 }; 167 168 CPU6:cpu@102 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x0 0x102>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 }; 175 176 CPU7:cpu@103 { 177 device_type = "cpu"; 178 compatible = "arm,armv8"; 179 reg = <0x0 0x103>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 182 }; 183 }; 184 185 memory@80000000 { 186 device_type = "memory"; 187 reg = <0x00000000 0x80000000 0 0x7F000000>, 188 <0x00000008 0x80000000 0 0x80000000>; 189 }; 190 191 gic: interrupt-controller@2f000000 { 192 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 193 #interrupt-cells = <3>; 194 #address-cells = <0>; 195 interrupt-controller; 196 reg = <0x0 0x2f000000 0 0x10000>, 197 <0x0 0x2c000000 0 0x2000>, 198 <0x0 0x2c010000 0 0x2000>, 199 <0x0 0x2c02F000 0 0x2000>; 200 interrupts = <1 9 0xf04>; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <1 13 0xff01>, 206 <1 14 0xff01>, 207 <1 11 0xff01>, 208 <1 10 0xff01>; 209 clock-frequency = <100000000>; 210 }; 211 212 timer@2a810000 { 213 compatible = "arm,armv7-timer-mem"; 214 reg = <0x0 0x2a810000 0x0 0x10000>; 215 clock-frequency = <100000000>; 216 #address-cells = <2>; 217 #size-cells = <2>; 218 ranges; 219 frame@2a830000 { 220 frame-number = <1>; 221 interrupts = <0 26 4>; 222 reg = <0x0 0x2a830000 0x0 0x10000>; 223 }; 224 }; 225 226 pmu { 227 compatible = "arm,armv8-pmuv3"; 228 interrupts = <0 60 4>, 229 <0 61 4>, 230 <0 62 4>, 231 <0 63 4>; 232 }; 233 234 smb { 235 compatible = "simple-bus"; 236 237 #address-cells = <2>; 238 #size-cells = <1>; 239 ranges = <0 0 0 0x08000000 0x04000000>, 240 <1 0 0 0x14000000 0x04000000>, 241 <2 0 0 0x18000000 0x04000000>, 242 <3 0 0 0x1c000000 0x04000000>, 243 <4 0 0 0x0c000000 0x04000000>, 244 <5 0 0 0x10000000 0x04000000>; 245 246 #interrupt-cells = <1>; 247 interrupt-map-mask = <0 0 63>; 248 interrupt-map = <0 0 0 &gic 0 0 4>, 249 <0 0 1 &gic 0 1 4>, 250 <0 0 2 &gic 0 2 4>, 251 <0 0 3 &gic 0 3 4>, 252 <0 0 4 &gic 0 4 4>, 253 <0 0 5 &gic 0 5 4>, 254 <0 0 6 &gic 0 6 4>, 255 <0 0 7 &gic 0 7 4>, 256 <0 0 8 &gic 0 8 4>, 257 <0 0 9 &gic 0 9 4>, 258 <0 0 10 &gic 0 10 4>, 259 <0 0 11 &gic 0 11 4>, 260 <0 0 12 &gic 0 12 4>, 261 <0 0 13 &gic 0 13 4>, 262 <0 0 14 &gic 0 14 4>, 263 <0 0 15 &gic 0 15 4>, 264 <0 0 16 &gic 0 16 4>, 265 <0 0 17 &gic 0 17 4>, 266 <0 0 18 &gic 0 18 4>, 267 <0 0 19 &gic 0 19 4>, 268 <0 0 20 &gic 0 20 4>, 269 <0 0 21 &gic 0 21 4>, 270 <0 0 22 &gic 0 22 4>, 271 <0 0 23 &gic 0 23 4>, 272 <0 0 24 &gic 0 24 4>, 273 <0 0 25 &gic 0 25 4>, 274 <0 0 26 &gic 0 26 4>, 275 <0 0 27 &gic 0 27 4>, 276 <0 0 28 &gic 0 28 4>, 277 <0 0 29 &gic 0 29 4>, 278 <0 0 30 &gic 0 30 4>, 279 <0 0 31 &gic 0 31 4>, 280 <0 0 32 &gic 0 32 4>, 281 <0 0 33 &gic 0 33 4>, 282 <0 0 34 &gic 0 34 4>, 283 <0 0 35 &gic 0 35 4>, 284 <0 0 36 &gic 0 36 4>, 285 <0 0 37 &gic 0 37 4>, 286 <0 0 38 &gic 0 38 4>, 287 <0 0 39 &gic 0 39 4>, 288 <0 0 40 &gic 0 40 4>, 289 <0 0 41 &gic 0 41 4>, 290 <0 0 42 &gic 0 42 4>; 291 292 /include/ "rtsm_ve-motherboard.dtsi" 293 }; 294 295 panels { 296 panel@0 { 297 compatible = "panel"; 298 mode = "XVGA"; 299 refresh = <60>; 300 xres = <1024>; 301 yres = <768>; 302 pixclock = <15748>; 303 left_margin = <152>; 304 right_margin = <48>; 305 upper_margin = <23>; 306 lower_margin = <3>; 307 hsync_len = <104>; 308 vsync_len = <4>; 309 sync = <0>; 310 vmode = "FB_VMODE_NONINTERLACED"; 311 tim2 = "TIM2_BCD", "TIM2_IPC"; 312 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 313 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 314 bpp = <16>; 315 }; 316 }; 317 }; 318
