1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of the ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /dts-v1/; 32 33 /memreserve/ 0x80000000 0x00010000; 34 35 / { 36 }; 37 38 / { 39 model = "FVP Foundation"; 40 compatible = "arm,fvp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { }; 46 47 aliases { 48 serial0 = &v2m_serial0; 49 serial1 = &v2m_serial1; 50 serial2 = &v2m_serial2; 51 serial3 = &v2m_serial3; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 56 method = "smc"; 57 cpu_suspend = <0xc4000001>; 58 cpu_off = <0x84000002>; 59 cpu_on = <0xc4000003>; 60 sys_poweroff = <0x84000008>; 61 sys_reset = <0x84000009>; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 }; 83 }; 84 85 idle-states { 86 entry-method = "arm,psci"; 87 88 CPU_SLEEP_0: cpu-sleep-0 { 89 compatible = "arm,idle-state"; 90 entry-method-param = <0x0010000>; 91 entry-latency-us = <40>; 92 exit-latency-us = <100>; 93 min-residency-us = <150>; 94 }; 95 96 CLUSTER_SLEEP_0: cluster-sleep-0 { 97 compatible = "arm,idle-state"; 98 entry-method-param = <0x1010000>; 99 entry-latency-us = <500>; 100 exit-latency-us = <1000>; 101 min-residency-us = <2500>; 102 }; 103 }; 104 105 CPU0:cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,armv8"; 108 reg = <0x0 0x0>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 111 }; 112 113 CPU1:cpu@1 { 114 device_type = "cpu"; 115 compatible = "arm,armv8"; 116 reg = <0x0 0x1>; 117 enable-method = "psci"; 118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 119 }; 120 121 CPU2:cpu@2 { 122 device_type = "cpu"; 123 compatible = "arm,armv8"; 124 reg = <0x0 0x2>; 125 enable-method = "psci"; 126 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 127 }; 128 129 CPU3:cpu@3 { 130 device_type = "cpu"; 131 compatible = "arm,armv8"; 132 reg = <0x0 0x3>; 133 enable-method = "psci"; 134 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 135 }; 136 }; 137 138 memory@80000000 { 139 device_type = "memory"; 140 reg = <0x00000000 0x80000000 0 0x7F000000>, 141 <0x00000008 0x80000000 0 0x80000000>; 142 }; 143 144 gic: interrupt-controller@2f000000 { 145 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 146 #interrupt-cells = <3>; 147 #address-cells = <0>; 148 interrupt-controller; 149 reg = <0x0 0x2f000000 0 0x10000>, 150 <0x0 0x2c000000 0 0x2000>, 151 <0x0 0x2c010000 0 0x2000>, 152 <0x0 0x2c02F000 0 0x2000>; 153 interrupts = <1 9 0xf04>; 154 }; 155 156 timer { 157 compatible = "arm,armv8-timer"; 158 interrupts = <1 13 0xff01>, 159 <1 14 0xff01>, 160 <1 11 0xff01>, 161 <1 10 0xff01>; 162 clock-frequency = <100000000>; 163 }; 164 165 timer@2a810000 { 166 compatible = "arm,armv7-timer-mem"; 167 reg = <0x0 0x2a810000 0x0 0x10000>; 168 clock-frequency = <100000000>; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 frame@2a830000 { 173 frame-number = <1>; 174 interrupts = <0 26 4>; 175 reg = <0x0 0x2a830000 0x0 0x10000>; 176 }; 177 }; 178 179 pmu { 180 compatible = "arm,armv8-pmuv3"; 181 interrupts = <0 60 4>, 182 <0 61 4>, 183 <0 62 4>, 184 <0 63 4>; 185 }; 186 187 smb { 188 compatible = "simple-bus"; 189 190 #address-cells = <2>; 191 #size-cells = <1>; 192 ranges = <0 0 0 0x08000000 0x04000000>, 193 <1 0 0 0x14000000 0x04000000>, 194 <2 0 0 0x18000000 0x04000000>, 195 <3 0 0 0x1c000000 0x04000000>, 196 <4 0 0 0x0c000000 0x04000000>, 197 <5 0 0 0x10000000 0x04000000>; 198 199 #interrupt-cells = <1>; 200 interrupt-map-mask = <0 0 63>; 201 interrupt-map = <0 0 0 &gic 0 0 4>, 202 <0 0 1 &gic 0 1 4>, 203 <0 0 2 &gic 0 2 4>, 204 <0 0 3 &gic 0 3 4>, 205 <0 0 4 &gic 0 4 4>, 206 <0 0 5 &gic 0 5 4>, 207 <0 0 6 &gic 0 6 4>, 208 <0 0 7 &gic 0 7 4>, 209 <0 0 8 &gic 0 8 4>, 210 <0 0 9 &gic 0 9 4>, 211 <0 0 10 &gic 0 10 4>, 212 <0 0 11 &gic 0 11 4>, 213 <0 0 12 &gic 0 12 4>, 214 <0 0 13 &gic 0 13 4>, 215 <0 0 14 &gic 0 14 4>, 216 <0 0 15 &gic 0 15 4>, 217 <0 0 16 &gic 0 16 4>, 218 <0 0 17 &gic 0 17 4>, 219 <0 0 18 &gic 0 18 4>, 220 <0 0 19 &gic 0 19 4>, 221 <0 0 20 &gic 0 20 4>, 222 <0 0 21 &gic 0 21 4>, 223 <0 0 22 &gic 0 22 4>, 224 <0 0 23 &gic 0 23 4>, 225 <0 0 24 &gic 0 24 4>, 226 <0 0 25 &gic 0 25 4>, 227 <0 0 26 &gic 0 26 4>, 228 <0 0 27 &gic 0 27 4>, 229 <0 0 28 &gic 0 28 4>, 230 <0 0 29 &gic 0 29 4>, 231 <0 0 30 &gic 0 30 4>, 232 <0 0 31 &gic 0 31 4>, 233 <0 0 32 &gic 0 32 4>, 234 <0 0 33 &gic 0 33 4>, 235 <0 0 34 &gic 0 34 4>, 236 <0 0 35 &gic 0 35 4>, 237 <0 0 36 &gic 0 36 4>, 238 <0 0 37 &gic 0 37 4>, 239 <0 0 38 &gic 0 38 4>, 240 <0 0 39 &gic 0 39 4>, 241 <0 0 40 &gic 0 40 4>, 242 <0 0 41 &gic 0 41 4>, 243 <0 0 42 &gic 0 42 4>; 244 245 /include/ "fvp-foundation-motherboard.dtsi" 246 }; 247 }; 248
