1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /dts-v1/; 32 33 /memreserve/ 0x80000000 0x00010000; 34 35 / { 36 }; 37 38 / { 39 model = "FVP Foundation"; 40 compatible = "arm,fvp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { }; 46 47 aliases { 48 serial0 = &v2m_serial0; 49 serial1 = &v2m_serial1; 50 serial2 = &v2m_serial2; 51 serial3 = &v2m_serial3; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 56 method = "smc"; 57 cpu_suspend = <0xc4000001>; 58 cpu_off = <0x84000002>; 59 cpu_on = <0xc4000003>; 60 }; 61 62 cpus { 63 #address-cells = <2>; 64 #size-cells = <0>; 65 66 cpu-map { 67 cluster0 { 68 core0 { 69 cpu = <&CPU0>; 70 }; 71 core1 { 72 cpu = <&CPU1>; 73 }; 74 core2 { 75 cpu = <&CPU2>; 76 }; 77 core3 { 78 cpu = <&CPU3>; 79 }; 80 }; 81 }; 82 83 idle-states { 84 entry-method = "arm,psci"; 85 86 CPU_SLEEP_0: cpu-sleep-0 { 87 compatible = "arm,idle-state"; 88 entry-method-param = <0x0010000>; 89 entry-latency-us = <40>; 90 exit-latency-us = <100>; 91 min-residency-us = <150>; 92 }; 93 94 CLUSTER_SLEEP_0: cluster-sleep-0 { 95 compatible = "arm,idle-state"; 96 entry-method-param = <0x1010000>; 97 entry-latency-us = <500>; 98 exit-latency-us = <1000>; 99 min-residency-us = <2500>; 100 }; 101 }; 102 103 CPU0:cpu@0 { 104 device_type = "cpu"; 105 compatible = "arm,armv8"; 106 reg = <0x0 0x0>; 107 enable-method = "psci"; 108 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 109 }; 110 111 CPU1:cpu@1 { 112 device_type = "cpu"; 113 compatible = "arm,armv8"; 114 reg = <0x0 0x1>; 115 enable-method = "psci"; 116 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 117 }; 118 119 CPU2:cpu@2 { 120 device_type = "cpu"; 121 compatible = "arm,armv8"; 122 reg = <0x0 0x2>; 123 enable-method = "psci"; 124 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 125 }; 126 127 CPU3:cpu@3 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 reg = <0x0 0x3>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 133 }; 134 }; 135 136 memory@80000000 { 137 device_type = "memory"; 138 reg = <0x00000000 0x80000000 0 0x7F000000>, 139 <0x00000008 0x80000000 0 0x80000000>; 140 }; 141 142 gic: interrupt-controller@2f000000 { 143 compatible = "arm,gic-v3"; 144 #interrupt-cells = <3>; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 interrupt-controller; 149 reg = <0x0 0x2f000000 0 0x10000>, // GICD 150 <0x0 0x2f100000 0 0x200000>, // GICR 151 <0x0 0x2c000000 0 0x2000>, // GICC 152 <0x0 0x2c010000 0 0x2000>, // GICH 153 <0x0 0x2c02f000 0 0x2000>; // GICV 154 interrupts = <1 9 4>; 155 156 its: its@2f020000 { 157 compatible = "arm,gic-v3-its"; 158 msi-controller; 159 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv8-timer"; 165 interrupts = <1 13 0xff01>, 166 <1 14 0xff01>, 167 <1 11 0xff01>, 168 <1 10 0xff01>; 169 clock-frequency = <100000000>; 170 }; 171 172 timer@2a810000 { 173 compatible = "arm,armv7-timer-mem"; 174 reg = <0x0 0x2a810000 0x0 0x10000>; 175 clock-frequency = <100000000>; 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 frame@2a830000 { 180 frame-number = <1>; 181 interrupts = <0 26 4>; 182 reg = <0x0 0x2a830000 0x0 0x10000>; 183 }; 184 }; 185 186 pmu { 187 compatible = "arm,armv8-pmuv3"; 188 interrupts = <0 60 4>, 189 <0 61 4>, 190 <0 62 4>, 191 <0 63 4>; 192 }; 193 194 smb { 195 compatible = "simple-bus"; 196 197 #address-cells = <2>; 198 #size-cells = <1>; 199 ranges = <0 0 0 0x08000000 0x04000000>, 200 <1 0 0 0x14000000 0x04000000>, 201 <2 0 0 0x18000000 0x04000000>, 202 <3 0 0 0x1c000000 0x04000000>, 203 <4 0 0 0x0c000000 0x04000000>, 204 <5 0 0 0x10000000 0x04000000>; 205 206 #interrupt-cells = <1>; 207 interrupt-map-mask = <0 0 63>; 208 interrupt-map = <0 0 0 &gic 0 0 0 0 4>, 209 <0 0 1 &gic 0 0 0 1 4>, 210 <0 0 2 &gic 0 0 0 2 4>, 211 <0 0 3 &gic 0 0 0 3 4>, 212 <0 0 4 &gic 0 0 0 4 4>, 213 <0 0 5 &gic 0 0 0 5 4>, 214 <0 0 6 &gic 0 0 0 6 4>, 215 <0 0 7 &gic 0 0 0 7 4>, 216 <0 0 8 &gic 0 0 0 8 4>, 217 <0 0 9 &gic 0 0 0 9 4>, 218 <0 0 10 &gic 0 0 0 10 4>, 219 <0 0 11 &gic 0 0 0 11 4>, 220 <0 0 12 &gic 0 0 0 12 4>, 221 <0 0 13 &gic 0 0 0 13 4>, 222 <0 0 14 &gic 0 0 0 14 4>, 223 <0 0 15 &gic 0 0 0 15 4>, 224 <0 0 16 &gic 0 0 0 16 4>, 225 <0 0 17 &gic 0 0 0 17 4>, 226 <0 0 18 &gic 0 0 0 18 4>, 227 <0 0 19 &gic 0 0 0 19 4>, 228 <0 0 20 &gic 0 0 0 20 4>, 229 <0 0 21 &gic 0 0 0 21 4>, 230 <0 0 22 &gic 0 0 0 22 4>, 231 <0 0 23 &gic 0 0 0 23 4>, 232 <0 0 24 &gic 0 0 0 24 4>, 233 <0 0 25 &gic 0 0 0 25 4>, 234 <0 0 26 &gic 0 0 0 26 4>, 235 <0 0 27 &gic 0 0 0 27 4>, 236 <0 0 28 &gic 0 0 0 28 4>, 237 <0 0 29 &gic 0 0 0 29 4>, 238 <0 0 30 &gic 0 0 0 30 4>, 239 <0 0 31 &gic 0 0 0 31 4>, 240 <0 0 32 &gic 0 0 0 32 4>, 241 <0 0 33 &gic 0 0 0 33 4>, 242 <0 0 34 &gic 0 0 0 34 4>, 243 <0 0 35 &gic 0 0 0 35 4>, 244 <0 0 36 &gic 0 0 0 36 4>, 245 <0 0 37 &gic 0 0 0 37 4>, 246 <0 0 38 &gic 0 0 0 38 4>, 247 <0 0 39 &gic 0 0 0 39 4>, 248 <0 0 40 &gic 0 0 0 40 4>, 249 <0 0 41 &gic 0 0 0 41 4>, 250 <0 0 42 &gic 0 0 0 42 4>; 251 252 /include/ "fvp-foundation-motherboard-no_psci.dtsi" 253 }; 254 }; 255
