1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PL011_H__ 32 #define __PL011_H__ 33 34 /* PL011 Registers */ 35 #define UARTDR 0x000 36 #define UARTRSR 0x004 37 #define UARTECR 0x004 38 #define UARTFR 0x018 39 #define UARTILPR 0x020 40 #define UARTIBRD 0x024 41 #define UARTFBRD 0x028 42 #define UARTLCR_H 0x02C 43 #define UARTCR 0x030 44 #define UARTIFLS 0x034 45 #define UARTIMSC 0x038 46 #define UARTRIS 0x03C 47 #define UARTMIS 0x040 48 #define UARTICR 0x044 49 #define UARTDMACR 0x048 50 51 /* Data status bits */ 52 #define UART_DATA_ERROR_MASK 0x0F00 53 54 /* Status reg bits */ 55 #define UART_STATUS_ERROR_MASK 0x0F 56 57 /* Flag reg bits */ 58 #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ 59 #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ 60 #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ 61 #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ 62 #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ 63 #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ 64 #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ 65 #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ 66 #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ 67 68 #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ 69 #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ 70 71 /* Control reg bits */ 72 #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ 73 #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ 74 #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ 75 #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ 76 #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ 77 #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ 78 #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ 79 #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ 80 81 #if !defined(PL011_LINE_CONTROL) 82 /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ 83 #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) 84 #endif 85 86 /* Line Control Register Bits */ 87 #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ 88 #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 89 #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 90 #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 91 #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 92 #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ 93 #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ 94 #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ 95 #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ 96 #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ 97 98 #endif /* __PL011_H__ */ 99
