1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CORTEX_A57_H__ 32 #define __CORTEX_A57_H__ 33 34 /* Cortex-A57 midr for revision 0 */ 35 #define CORTEX_A57_MIDR 0x410FD070 36 37 /******************************************************************************* 38 * CPU Extended Control register specific definitions. 39 ******************************************************************************/ 40 #define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ 41 42 #define CPUECTLR_SMP_BIT (1 << 6) 43 #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) 44 #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) 45 #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) 46 47 /******************************************************************************* 48 * CPU Auxiliary Control register specific definitions. 49 ******************************************************************************/ 50 #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ 51 52 #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) 53 #define CPUACTLR_DCC_AS_DCCI (1 << 44) 54 55 /******************************************************************************* 56 * L2 Control register specific definitions. 57 ******************************************************************************/ 58 #define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ 59 60 #define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 61 #define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 62 63 #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 64 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 65 66 #endif /* __CORTEX_A57_H__ */ 67
