1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <aem_generic.h> 31 #include <arch.h> 32 #include <asm_macros.S> 33 #include <cpu_macros.S> 34 35 func aem_generic_core_pwr_dwn 36 /* --------------------------------------------- 37 * Disable the Data Cache. 38 * --------------------------------------------- 39 */ 40 mrs x1, sctlr_el3 41 bic x1, x1, #SCTLR_C_BIT 42 msr sctlr_el3, x1 43 isb 44 45 mov x0, #DCCISW 46 47 /* --------------------------------------------- 48 * Flush L1 cache to PoU. 49 * --------------------------------------------- 50 */ 51 b dcsw_op_louis 52 53 54 func aem_generic_cluster_pwr_dwn 55 /* --------------------------------------------- 56 * Disable the Data Cache. 57 * --------------------------------------------- 58 */ 59 mrs x1, sctlr_el3 60 bic x1, x1, #SCTLR_C_BIT 61 msr sctlr_el3, x1 62 isb 63 64 /* --------------------------------------------- 65 * Flush L1 and L2 caches to PoC. 66 * --------------------------------------------- 67 */ 68 mov x0, #DCCISW 69 b dcsw_op_all 70 71 /* --------------------------------------------- 72 * This function provides cpu specific 73 * register information for crash reporting. 74 * It needs to return with x6 pointing to 75 * a list of register names in ascii and 76 * x8 - x15 having values of registers to be 77 * reported. 78 * --------------------------------------------- 79 */ 80 func aem_generic_cpu_reg_dump 81 mov x6, #0 /* no registers to report */ 82 ret 83 84 85 /* cpu_ops for Base AEM FVP */ 86 declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 87 88 /* cpu_ops for Foundation FVP */ 89 declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1 90
