1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <asm_macros.S> 33 #include <assert_macros.S> 34 #include <cpu_macros.S> 35 #if IMAGE_BL31 36 #include <cpu_data.h> 37 #endif 38 39 /* Reset fn is needed in BL at reset vector */ 40 #if IMAGE_BL1 || IMAGE_BL31 41 /* 42 * The reset handler common to all platforms. After a matching 43 * cpu_ops structure entry is found, the correponding reset_handler 44 * in the cpu_ops is invoked. 45 * Clobbers: x0 - x19, x30 46 */ 47 .globl reset_handler 48 func reset_handler 49 mov x19, x30 50 51 /* The plat_reset_handler can clobber x0 - x18, x30 */ 52 bl plat_reset_handler 53 54 /* Get the matching cpu_ops pointer */ 55 bl get_cpu_ops_ptr 56 #if ASM_ASSERTION 57 cmp x0, #0 58 ASM_ASSERT(ne) 59 #endif 60 61 /* Get the cpu_ops reset handler */ 62 ldr x2, [x0, #CPU_RESET_FUNC] 63 mov x30, x19 64 cbz x2, 1f 65 66 /* The cpu_ops reset handler can clobber x0 - x19, x30 */ 67 br x2 68 1: 69 ret 70 71 #endif /* IMAGE_BL1 || IMAGE_BL31 */ 72 73 #if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ 74 /* 75 * The prepare core power down function for all platforms. After 76 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 77 * pwr_dwn_core in the cpu_ops is invoked. 78 */ 79 .globl prepare_core_pwr_dwn 80 func prepare_core_pwr_dwn 81 mrs x1, tpidr_el3 82 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] 83 #if ASM_ASSERTION 84 cmp x0, #0 85 ASM_ASSERT(ne) 86 #endif 87 88 /* Get the cpu_ops core_pwr_dwn handler */ 89 ldr x1, [x0, #CPU_PWR_DWN_CORE] 90 br x1 91 92 /* 93 * The prepare cluster power down function for all platforms. After 94 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 95 * pwr_dwn_cluster in the cpu_ops is invoked. 96 */ 97 .globl prepare_cluster_pwr_dwn 98 func prepare_cluster_pwr_dwn 99 mrs x1, tpidr_el3 100 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] 101 #if ASM_ASSERTION 102 cmp x0, #0 103 ASM_ASSERT(ne) 104 #endif 105 106 /* Get the cpu_ops cluster_pwr_dwn handler */ 107 ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] 108 br x1 109 110 111 /* 112 * Initializes the cpu_ops_ptr if not already initialized 113 * in cpu_data. This can be called without a runtime stack. 114 * clobbers: x0 - x6, x10 115 */ 116 .globl init_cpu_ops 117 func init_cpu_ops 118 mrs x6, tpidr_el3 119 ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] 120 cbnz x0, 1f 121 mov x10, x30 122 bl get_cpu_ops_ptr 123 #if ASM_ASSERTION 124 cmp x0, #0 125 ASM_ASSERT(ne) 126 #endif 127 str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! 128 129 /* 130 * Make sure that any pre-fetched cache copies are invalidated. 131 * Ensure that we are running with cache disable else we 132 * invalidate our own update. 133 */ 134 #if ASM_ASSERTION 135 mrs x1, sctlr_el3 136 tst x1, #SCTLR_C_BIT 137 ASM_ASSERT(eq) 138 #endif 139 dc ivac, x6 140 mov x30, x10 141 1: 142 ret 143 #endif /* IMAGE_BL31 */ 144 145 #if IMAGE_BL31 && CRASH_REPORTING 146 /* 147 * The cpu specific registers which need to be reported in a crash 148 * are reported via cpu_ops cpu_reg_dump function. After a matching 149 * cpu_ops structure entry is found, the correponding cpu_reg_dump 150 * in the cpu_ops is invoked. 151 */ 152 .globl do_cpu_reg_dump 153 func do_cpu_reg_dump 154 mov x16, x30 155 156 /* Get the matching cpu_ops pointer */ 157 bl get_cpu_ops_ptr 158 cbz x0, 1f 159 160 /* Get the cpu_ops cpu_reg_dump */ 161 ldr x2, [x0, #CPU_REG_DUMP] 162 cbz x2, 1f 163 blr x2 164 1: 165 mov x30, x16 166 ret 167 #endif 168 169 /* 170 * The below function returns the cpu_ops structure matching the 171 * midr of the core. It reads the MIDR_EL1 and finds the matching 172 * entry in cpu_ops entries. Only the implementation and part number 173 * are used to match the entries. 174 * Return : 175 * x0 - The matching cpu_ops pointer on Success 176 * x0 - 0 on failure. 177 * Clobbers : x0 - x5 178 */ 179 .globl get_cpu_ops_ptr 180 func get_cpu_ops_ptr 181 /* Get the cpu_ops start and end locations */ 182 adr x4, (__CPU_OPS_START__ + CPU_MIDR) 183 adr x5, (__CPU_OPS_END__ + CPU_MIDR) 184 185 /* Initialize the return parameter */ 186 mov x0, #0 187 188 /* Read the MIDR_EL1 */ 189 mrs x2, midr_el1 190 mov_imm x3, CPU_IMPL_PN_MASK 191 192 /* Retain only the implementation and part number using mask */ 193 and w2, w2, w3 194 1: 195 /* Check if we have reached end of list */ 196 cmp x4, x5 197 b.eq error_exit 198 199 /* load the midr from the cpu_ops */ 200 ldr x1, [x4], #CPU_OPS_SIZE 201 and w1, w1, w3 202 203 /* Check if midr matches to midr of this core */ 204 cmp w1, w2 205 b.ne 1b 206 207 /* Subtract the increment and offset to get the cpu-ops pointer */ 208 sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) 209 error_exit: 210 ret 211 212 #if DEBUG 213 /* 214 * This function prints a warning message to the crash console 215 * if the CPU revision/part number does not match the errata 216 * workaround enabled in the build. 217 * Clobber: x30, x0 - x5 218 */ 219 .section .rodata.rev_warn_str, "aS" 220 rev_warn_str: 221 .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" 222 223 .globl print_revision_warning 224 func print_revision_warning 225 mov x5, x30 226 /* Ensure the console is initialized */ 227 bl plat_crash_console_init 228 /* Check if the console is initialized */ 229 cbz x0, 1f 230 /* The console is initialized */ 231 adr x4, rev_warn_str 232 bl asm_print_str 233 1: 234 ret x5 235 #endif 236 237
