1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <bakery_lock.h> 33 #include <mmio.h> 34 #include <hisi_ipc.h> 35 #include <hisi_pwrc.h> 36 #include <hisi_sram_map.h> 37 #include <hi6220_regs_acpu.h> 38 #include <stdio.h> 39 #include <stdarg.h> 40 #include <string.h> 41 #include <platform_def.h> 42 43 #define CLUSTER_CORE_COUNT (4) 44 #define CLUSTER_CORE_MASK ((1 << CLUSTER_CORE_COUNT) - 1) 45 46 #define BIT(x) (0x1 << (x)) 47 48 void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, 49 uintptr_t entry_point) 50 { 51 uintptr_t *core_entry = (uintptr_t *)PWRCTRL_ACPU_ASM_D_ARM_PARA_AD; 52 unsigned int i; 53 54 if (!core_entry) { 55 printf("%s: core entry point is null!\n", __func__); 56 return; 57 } 58 59 i = cluster * CLUSTER_CORE_COUNT + core; 60 mmio_write_64((uintptr_t)(core_entry + i), entry_point); 61 } 62 63 void hisi_pwrc_set_cluster_wfi(unsigned int cluster) 64 { 65 unsigned int reg = 0; 66 67 if (cluster == 0) { 68 reg = mmio_read_32(ACPU_CTRL_BASE + 0x0E4); 69 reg |= BIT(0); 70 mmio_write_32(ACPU_CTRL_BASE + 0x0E4, reg); 71 } else if (cluster == 1) { 72 reg = mmio_read_32(ACPU_CTRL_BASE + 0x0E4); 73 reg |= BIT(16); 74 mmio_write_32(ACPU_CTRL_BASE + 0x0E4, reg); 75 } 76 } 77 78 int hisi_pwrc_setup(void) 79 { 80 unsigned int reg; 81 extern char pm_asm_code[], pm_asm_code_end[]; 82 extern char v7_asm[], v7_asm_end[]; 83 84 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 85 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 86 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 87 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 88 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 89 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 90 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 91 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), PWRCTRL_ACPU_ASM_CODE_BASE >> 2); 92 93 memset((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, 0, 0x400); 94 memcpy((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, (void *)v7_asm, 95 v7_asm_end - v7_asm); 96 97 memcpy((void *)PWRCTRL_ACPU_ASM_CODE_BASE, (void *)pm_asm_code, 98 pm_asm_code_end - pm_asm_code); 99 100 reg = mmio_read_32(0xF7800000 + 0x004); 101 reg |= BIT(0x1) | BIT(17); 102 mmio_write_32(0xF7800000 + 0x004, reg); 103 104 return 0; 105 } 106
