1 #------------------------------------------------------------------------------ 2 # 3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. 5 # 6 # This program and the accompanying materials 7 # are licensed and made available under the terms and conditions of the BSD License 8 # which accompanies this distribution. The full text of the license may be found at 9 # http://opensource.org/licenses/bsd-license.php 10 # 11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 # 14 #------------------------------------------------------------------------------ 15 16 #include <AsmMacroIoLibV8.h> 17 18 .text 19 .align 3 20 GCC_ASM_EXPORT (ArmReadMidr) 21 GCC_ASM_EXPORT (ArmCacheInfo) 22 GCC_ASM_EXPORT (ArmGetInterruptState) 23 GCC_ASM_EXPORT (ArmGetFiqState) 24 GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress) 25 GCC_ASM_EXPORT (ArmSetTTBR0) 26 GCC_ASM_EXPORT (ArmGetTCR) 27 GCC_ASM_EXPORT (ArmSetTCR) 28 GCC_ASM_EXPORT (ArmGetMAIR) 29 GCC_ASM_EXPORT (ArmSetMAIR) 30 GCC_ASM_EXPORT (ArmWriteCpacr) 31 GCC_ASM_EXPORT (ArmWriteAuxCr) 32 GCC_ASM_EXPORT (ArmReadAuxCr) 33 GCC_ASM_EXPORT (ArmInvalidateTlb) 34 GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry) 35 GCC_ASM_EXPORT (ArmWriteCptr) 36 GCC_ASM_EXPORT (ArmWriteScr) 37 GCC_ASM_EXPORT (ArmWriteMVBar) 38 GCC_ASM_EXPORT (ArmCallWFE) 39 GCC_ASM_EXPORT (ArmCallSEV) 40 GCC_ASM_EXPORT (ArmReadCpuActlr) 41 GCC_ASM_EXPORT (ArmWriteCpuActlr) 42 43 #------------------------------------------------------------------------------ 44 45 .set DAIF_FIQ_BIT, (1 << 0) 46 .set DAIF_IRQ_BIT, (1 << 1) 47 48 ASM_PFX(ArmReadMidr): 49 mrs x0, midr_el1 // Read from Main ID Register (MIDR) 50 ret 51 52 ASM_PFX(ArmCacheInfo): 53 mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR) 54 ret 55 56 ASM_PFX(ArmGetInterruptState): 57 mrs x0, daif 58 tst w0, #DAIF_IRQ_BIT // Check if IRQ is enabled. Enabled if 0. 59 mov w0, #0 60 mov w1, #1 61 csel w0, w1, w0, ne 62 ret 63 64 ASM_PFX(ArmGetFiqState): 65 mrs x0, daif 66 tst w0, #DAIF_FIQ_BIT // Check if FIQ is enabled. Enabled if 0. 67 mov w0, #0 68 mov w1, #1 69 csel w0, w1, w0, ne 70 ret 71 72 ASM_PFX(ArmWriteCpacr): 73 msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR) 74 ret 75 76 ASM_PFX(ArmWriteAuxCr): 77 EL1_OR_EL2(x1) 78 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 79 ret 80 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 81 ret 82 83 ASM_PFX(ArmReadAuxCr): 84 EL1_OR_EL2(x1) 85 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 86 ret 87 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3 88 ret 89 90 ASM_PFX(ArmSetTTBR0): 91 EL1_OR_EL2_OR_EL3(x1) 92 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0) 93 b 4f 94 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0) 95 b 4f 96 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0) 97 4:isb 98 ret 99 100 ASM_PFX(ArmGetTTBR0BaseAddress): 101 EL1_OR_EL2(x1) 102 1:mrs x0, ttbr0_el1 103 b 3f 104 2:mrs x0, ttbr0_el2 105 3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */ 106 and x0, x0, x1 107 isb 108 ret 109 110 ASM_PFX(ArmGetTCR): 111 EL1_OR_EL2_OR_EL3(x1) 112 1:mrs x0, tcr_el1 113 b 4f 114 2:mrs x0, tcr_el2 115 b 4f 116 3:mrs x0, tcr_el3 117 4:isb 118 ret 119 120 ASM_PFX(ArmSetTCR): 121 EL1_OR_EL2_OR_EL3(x1) 122 1:msr tcr_el1, x0 123 b 4f 124 2:msr tcr_el2, x0 125 b 4f 126 3:msr tcr_el3, x0 127 4:isb 128 ret 129 130 ASM_PFX(ArmGetMAIR): 131 EL1_OR_EL2_OR_EL3(x1) 132 1:mrs x0, mair_el1 133 b 4f 134 2:mrs x0, mair_el2 135 b 4f 136 3:mrs x0, mair_el3 137 4:isb 138 ret 139 140 ASM_PFX(ArmSetMAIR): 141 EL1_OR_EL2_OR_EL3(x1) 142 1:msr mair_el1, x0 143 b 4f 144 2:msr mair_el2, x0 145 b 4f 146 3:msr mair_el3, x0 147 4:isb 148 ret 149 150 151 // 152 //VOID 153 //ArmUpdateTranslationTableEntry ( 154 // IN VOID *TranslationTableEntry // X0 155 // IN VOID *MVA // X1 156 // ); 157 ASM_PFX(ArmUpdateTranslationTableEntry): 158 dc civac, x0 // Clean and invalidate data line 159 dsb sy 160 EL1_OR_EL2_OR_EL3(x0) 161 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 162 b 4f 163 2: tlbi vae2, x1 // TLB Invalidate VA , EL2 164 b 4f 165 3: tlbi vae3, x1 // TLB Invalidate VA , EL3 166 4: dsb sy 167 isb 168 ret 169 170 ASM_PFX(ArmInvalidateTlb): 171 EL1_OR_EL2_OR_EL3(x0) 172 1: tlbi vmalle1 173 b 4f 174 2: tlbi alle2 175 b 4f 176 3: tlbi alle3 177 4: dsb sy 178 isb 179 ret 180 181 ASM_PFX(ArmWriteCptr): 182 msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR) 183 ret 184 185 ASM_PFX(ArmWriteScr): 186 msr scr_el3, x0 // Secure configuration register EL3 187 ret 188 189 ASM_PFX(ArmWriteMVBar): 190 msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3 191 ret 192 193 ASM_PFX(ArmCallWFE): 194 wfe 195 ret 196 197 ASM_PFX(ArmCallSEV): 198 sev 199 ret 200 201 ASM_PFX(ArmReadCpuActlr): 202 mrs x0, S3_1_c15_c2_0 203 ret 204 205 ASM_PFX(ArmWriteCpuActlr): 206 msr S3_1_c15_c2_0, x0 207 dsb sy 208 isb 209 ret 210 211 ASM_FUNCTION_REMOVE_IF_UNREFERENCED 212
