1 #/** @file 2 # 3 # Copyright (c) 2011-2015, ARM Limited. All rights reserved. 4 # Copyright (c) 2015, Intel Corporation. All rights reserved. 5 # 6 # This program and the accompanying materials 7 # are licensed and made available under the terms and conditions of the BSD License 8 # which accompanies this distribution. The full text of the license may be found at 9 # http://opensource.org/licenses/bsd-license.php 10 # 11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 # 14 #**/ 15 16 [Defines] 17 DEC_SPECIFICATION = 0x00010005 18 PACKAGE_NAME = ArmPlatformPkg 19 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b 20 PACKAGE_VERSION = 0.1 21 22 ################################################################################ 23 # 24 # Include Section - list of Include Paths that are provided by this package. 25 # Comments are used for Keywords and Module Types. 26 # 27 # Supported Module Types: 28 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION 29 # 30 ################################################################################ 31 [Includes.common] 32 Include # Root include for the package 33 34 [Guids.common] 35 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } } 36 # 37 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf 38 # 39 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } 40 41 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } 42 43 [PcdsFeatureFlag.common] 44 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. 45 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 46 47 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 48 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002 49 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 50 51 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C 52 53 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE, 54 # we assume the OS will handle the FrameBuffer from the UEFI GOP information. 55 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D 56 57 # Enable Legacy Linux support in the BDS 58 gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E 59 60 [PcdsFixedAtBuild.common] 61 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 62 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 63 64 # Stack for CPU Cores in Secure Mode 65 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005 66 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 67 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 68 69 # Stack for CPU Cores in Non Secure Mode 70 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 71 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 72 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A 73 74 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) 75 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 76 77 # Boot Monitor FileSystem 78 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A 79 80 # 81 # ARM Primecells 82 # 83 84 ## SP804 DualTimer 85 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D 86 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E 87 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A 88 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B 89 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C 90 91 ## SP805 Watchdog 92 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023 93 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021 94 95 ## PL011 UART 96 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F 97 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 98 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D 99 100 ## PL061 GPIO 101 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025 102 103 ## PL111 Lcd & HdLcd 104 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 105 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 106 107 ## PL180 MCI 108 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 109 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 110 111 # 112 # BDS - Boot Manager 113 # 114 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019 115 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C 116 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D 117 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F 118 119 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B 120 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C 121 122 [PcdsFixedAtBuild.common,PcdsDynamic.common] 123 ## PL031 RealTimeClock 124 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 125 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 126 127 # 128 # Inclusive range of allowed PCI buses. 129 # 130 gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E 131 gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F 132 133 # 134 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. 135 # Note that "IO" is just another MMIO range that simulates IO space; there 136 # are no special instructions to access it. 137 # 138 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are 139 # specific to their containing address spaces. In order to get the physical 140 # address for the CPU, for a given access, the respective translation value 141 # has to be added. 142 # 143 # The translations always have to be initialized like this, using UINT64: 144 # 145 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space 146 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space 147 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space 148 # 149 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; 150 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; 151 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; 152 # 153 # because (a) the target address space (ie. the cpu-physical space) is 154 # 64-bit, and (b) the translation values are meant as offsets for *modular* 155 # arithmetic. 156 # 157 # Accordingly, the translation itself needs to be implemented as: 158 # 159 # UINT64 UntranslatedIoAddress; // input parameter 160 # UINT32 UntranslatedMmio32Address; // input parameter 161 # UINT64 UntranslatedMmio64Address; // input parameter 162 # 163 # UINT64 TranslatedIoAddress; // output parameter 164 # UINT64 TranslatedMmio32Address; // output parameter 165 # UINT64 TranslatedMmio64Address; // output parameter 166 # 167 # TranslatedIoAddress = UntranslatedIoAddress + 168 # PcdPciIoTranslation; 169 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + 170 # PcdPciMmio32Translation; 171 # TranslatedMmio64Address = UntranslatedMmio64Address + 172 # PcdPciMmio64Translation; 173 # 174 # The modular arithmetic performed in UINT64 ensures that the translation 175 # works correctly regardless of the relation between IoCpuBase and 176 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and 177 # PcdPciMmio64Base. 178 # 179 gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040 180 gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041 181 gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042 182 gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043 183 gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044 184 gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045 185 gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046 186 gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047 187 gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048 188 189 [PcdsFixedAtBuild.ARM] 190 # Stack for CPU Cores in Secure Monitor Mode 191 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007 192 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 193 194 [PcdsFixedAtBuild.AARCH64] 195 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. 196 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize 197 # and PcdCPUCoreSecSecondaryStackSize 198 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007 199 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 200 201
