1 /** @file 2 3 Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 **/ 13 14 #ifndef __LCDPLATFORMLIB_H 15 #define __LCDPLATFORMLIB_H 16 17 #include <Protocol/GraphicsOutput.h> 18 19 #define LCD_VRAM_SIZE SIZE_8MB 20 21 // 22 // Modes definitions 23 // 24 #define VGA 0 25 #define SVGA 1 26 #define XGA 2 27 #define SXGA 3 28 #define WSXGA 4 29 #define UXGA 5 30 #define HD 6 31 32 // 33 // VGA Mode: 640 x 480 34 // 35 #define VGA_H_RES_PIXELS 640 36 #define VGA_V_RES_PIXELS 480 37 #define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */ 38 39 #define VGA_H_SYNC ( 80 - 1) 40 #define VGA_H_FRONT_PORCH ( 16 - 1) 41 #define VGA_H_BACK_PORCH ( 64 - 1) 42 43 #define VGA_V_SYNC ( 4 - 1) 44 #define VGA_V_FRONT_PORCH ( 3 - 1) 45 #define VGA_V_BACK_PORCH ( 13 - 1) 46 47 // 48 // SVGA Mode: 800 x 600 49 // 50 #define SVGA_H_RES_PIXELS 800 51 #define SVGA_V_RES_PIXELS 600 52 #define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */ 53 54 #define SVGA_H_SYNC ( 80 - 1) 55 #define SVGA_H_FRONT_PORCH ( 32 - 1) 56 #define SVGA_H_BACK_PORCH (112 - 1) 57 58 #define SVGA_V_SYNC ( 4 - 1) 59 #define SVGA_V_FRONT_PORCH ( 3 - 1) 60 #define SVGA_V_BACK_PORCH ( 17 - 1) 61 62 // 63 // XGA Mode: 1024 x 768 64 // 65 #define XGA_H_RES_PIXELS 1024 66 #define XGA_V_RES_PIXELS 768 67 #define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */ 68 69 #define XGA_H_SYNC (104 - 1) 70 #define XGA_H_FRONT_PORCH ( 48 - 1) 71 #define XGA_H_BACK_PORCH (152 - 1) 72 73 #define XGA_V_SYNC ( 4 - 1) 74 #define XGA_V_FRONT_PORCH ( 3 - 1) 75 #define XGA_V_BACK_PORCH ( 23 - 1) 76 77 // 78 // SXGA Mode: 1280 x 1024 79 // 80 #define SXGA_H_RES_PIXELS 1280 81 #define SXGA_V_RES_PIXELS 1024 82 #define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */ 83 84 #define SXGA_H_SYNC (136 - 1) 85 #define SXGA_H_FRONT_PORCH ( 80 - 1) 86 #define SXGA_H_BACK_PORCH (216 - 1) 87 88 #define SXGA_V_SYNC ( 7 - 1) 89 #define SXGA_V_FRONT_PORCH ( 3 - 1) 90 #define SXGA_V_BACK_PORCH ( 29 - 1) 91 92 // 93 // WSXGA+ Mode: 1680 x 1050 94 // 95 #define WSXGA_H_RES_PIXELS 1680 96 #define WSXGA_V_RES_PIXELS 1050 97 #define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */ 98 99 #define WSXGA_H_SYNC (170 - 1) 100 #define WSXGA_H_FRONT_PORCH (104 - 1) 101 #define WSXGA_H_BACK_PORCH (274 - 1) 102 103 #define WSXGA_V_SYNC ( 5 - 1) 104 #define WSXGA_V_FRONT_PORCH ( 4 - 1) 105 #define WSXGA_V_BACK_PORCH ( 41 - 1) 106 107 // 108 // UXGA Mode: 1600 x 1200 109 // 110 #define UXGA_H_RES_PIXELS 1600 111 #define UXGA_V_RES_PIXELS 1200 112 #define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */ 113 114 #define UXGA_H_SYNC (168 - 1) 115 #define UXGA_H_FRONT_PORCH (112 - 1) 116 #define UXGA_H_BACK_PORCH (280 - 1) 117 118 #define UXGA_V_SYNC ( 4 - 1) 119 #define UXGA_V_FRONT_PORCH ( 3 - 1) 120 #define UXGA_V_BACK_PORCH ( 38 - 1) 121 122 // 123 // HD Mode: 1920 x 1080 124 // 125 #define HD_H_RES_PIXELS 1920 126 #define HD_V_RES_PIXELS 1080 127 #define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */ 128 129 #define HD_H_SYNC ( 79 - 1) 130 #define HD_H_FRONT_PORCH (128 - 1) 131 #define HD_H_BACK_PORCH (328 - 1) 132 133 #define HD_V_SYNC ( 5 - 1) 134 #define HD_V_FRONT_PORCH ( 3 - 1) 135 #define HD_V_BACK_PORCH ( 32 - 1) 136 137 // 138 // Colour Masks 139 // 140 141 #define LCD_24BPP_RED_MASK 0x00FF0000 142 #define LCD_24BPP_GREEN_MASK 0x0000FF00 143 #define LCD_24BPP_BLUE_MASK 0x000000FF 144 #define LCD_24BPP_RESERVED_MASK 0xFF000000 145 146 #define LCD_16BPP_555_RED_MASK 0x00007C00 147 #define LCD_16BPP_555_GREEN_MASK 0x000003E0 148 #define LCD_16BPP_555_BLUE_MASK 0x0000001F 149 #define LCD_16BPP_555_RESERVED_MASK 0x00000000 150 151 #define LCD_16BPP_565_RED_MASK 0x0000F800 152 #define LCD_16BPP_565_GREEN_MASK 0x000007E0 153 #define LCD_16BPP_565_BLUE_MASK 0x0000001F 154 #define LCD_16BPP_565_RESERVED_MASK 0x00008000 155 156 #define LCD_12BPP_444_RED_MASK 0x00000F00 157 #define LCD_12BPP_444_GREEN_MASK 0x000000F0 158 #define LCD_12BPP_444_BLUE_MASK 0x0000000F 159 #define LCD_12BPP_444_RESERVED_MASK 0x0000F000 160 161 162 // The enumeration indexes maps the PL111 LcdBpp values used in the LCD Control Register 163 typedef enum { 164 LCD_BITS_PER_PIXEL_1 = 0, 165 LCD_BITS_PER_PIXEL_2, 166 LCD_BITS_PER_PIXEL_4, 167 LCD_BITS_PER_PIXEL_8, 168 LCD_BITS_PER_PIXEL_16_555, 169 LCD_BITS_PER_PIXEL_24, 170 LCD_BITS_PER_PIXEL_16_565, 171 LCD_BITS_PER_PIXEL_12_444 172 } LCD_BPP; 173 174 175 EFI_STATUS 176 LcdPlatformInitializeDisplay ( 177 IN EFI_HANDLE Handle 178 ); 179 180 EFI_STATUS 181 LcdPlatformGetVram ( 182 OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, 183 OUT UINTN* VramSize 184 ); 185 186 UINT32 187 LcdPlatformGetMaxMode ( 188 VOID 189 ); 190 191 EFI_STATUS 192 LcdPlatformSetMode ( 193 IN UINT32 ModeNumber 194 ); 195 196 EFI_STATUS 197 LcdPlatformQueryMode ( 198 IN UINT32 ModeNumber, 199 OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info 200 ); 201 202 EFI_STATUS 203 LcdPlatformGetTimings ( 204 IN UINT32 ModeNumber, 205 OUT UINT32* HRes, 206 OUT UINT32* HSync, 207 OUT UINT32* HBackPorch, 208 OUT UINT32* HFrontPorch, 209 OUT UINT32* VRes, 210 OUT UINT32* VSync, 211 OUT UINT32* VBackPorch, 212 OUT UINT32* VFrontPorch 213 ); 214 215 EFI_STATUS 216 LcdPlatformGetBpp ( 217 IN UINT32 ModeNumber, 218 OUT LCD_BPP* Bpp 219 ); 220 221 #endif 222
