1 #======================================================================================== 2 # Copyright (c) 2011-2014, ARM Limited. All rights reserved. 3 # 4 # This program and the accompanying materials 5 # are licensed and made available under the terms and conditions of the BSD License 6 # which accompanies this distribution. The full text of the license may be found at 7 # http:#opensource.org/licenses/bsd-license.php 8 # 9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 # 12 #======================================================================================= 13 14 #include <AsmMacroIoLibV8.h> 15 #include <Chipset/AArch64.h> 16 17 #start of the code section 18 .text 19 .align 3 20 21 GCC_ASM_EXPORT(SwitchToNSExceptionLevel1) 22 GCC_ASM_EXPORT(enter_monitor_mode) 23 GCC_ASM_EXPORT(return_from_exception) 24 GCC_ASM_EXPORT(copy_cpsr_into_spsr) 25 GCC_ASM_EXPORT(set_non_secure_mode) 26 27 // Switch from EL3 to NS-EL1 28 ASM_PFX(SwitchToNSExceptionLevel1): 29 // Now setup our EL1. Controlled by EL2 config on Model 30 mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register 31 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit 32 33 // Send all interrupts to their respective Exception levels for EL2 34 and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort 35 msr hcr_el2, x0 // Write back our settings 36 37 msr cptr_el2, xzr // Disable copro traps to EL2 38 39 msr sctlr_el2, xzr 40 41 // Enable architected timer access 42 mrs x0, cnthctl_el2 43 orr x0, x0, #3 // Enable EL1 access to timers 44 msr cnthctl_el2, x0 45 46 mrs x0, cntkctl_el1 47 orr x0, x0, #3 // EL0 access to counters 48 msr cntkctl_el1, x0 49 50 // Set ID regs 51 mrs x0, midr_el1 52 mrs x1, mpidr_el1 53 msr vpidr_el2, x0 54 msr vmpidr_el2, x1 55 56 ret 57 58 59 // EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7 60 // we don't need a mode switch, just setup the Arguments and jump. 61 // x0: Monitor World EntryPoint 62 // x1: MpId 63 // x2: SecBootMode 64 // x3: Secure Monitor mode stack 65 ASM_PFX(enter_monitor_mode): 66 mov x4, x0 // Swap EntryPoint and MpId registers 67 mov x0, x1 68 mov x1, x2 69 mov x2, x3 70 br x4 71 72 // Put the address in correct ELR_ELx and do a eret. 73 // We may need to do some config before we change to another Mode. 74 ASM_PFX(return_from_exception): 75 msr elr_el3, x0 76 eret 77 78 // For AArch64 we need to construct the spsr we want from individual bits and pieces. 79 ASM_PFX(copy_cpsr_into_spsr): 80 mrs x0, CurrentEl // Get the current exception level we are running at. 81 mrs x1, SPSel // Which Stack are we using 82 orr x0, x0, x1 83 mrs x1, daif // Which interrupts are enabled 84 orr x0, x0, x1 85 msr spsr_el3, x0 // Write to spsr 86 ret 87 88 // Get this from platform file. 89 ASM_PFX(set_non_secure_mode): 90 msr spsr_el3, x0 91 ret 92 93 ASM_FUNCTION_REMOVE_IF_UNREFERENCED 94
