1 /*++ 2 3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 Module Name: 13 14 CpuIA32.h 15 16 Abstract: 17 18 --*/ 19 20 #ifndef _CPU_IA32_H 21 #define _CPU_IA32_H 22 23 #include "Tiano.h" 24 25 typedef struct { 26 UINT32 RegEax; 27 UINT32 RegEbx; 28 UINT32 RegEcx; 29 UINT32 RegEdx; 30 } EFI_CPUID_REGISTER; 31 32 typedef struct { 33 UINT32 HeaderVersion; 34 UINT32 UpdateRevision; 35 UINT32 Date; 36 UINT32 ProcessorId; 37 UINT32 Checksum; 38 UINT32 LoaderRevision; 39 UINT32 ProcessorFlags; 40 UINT32 DataSize; 41 UINT32 TotalSize; 42 UINT8 Reserved[12]; 43 } EFI_CPU_MICROCODE_HEADER; 44 45 typedef struct { 46 UINT32 ExtendedSignatureCount; 47 UINT32 ExtendedTableChecksum; 48 UINT8 Reserved[12]; 49 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER; 50 51 typedef struct { 52 UINT32 ProcessorSignature; 53 UINT32 ProcessorFlag; 54 UINT32 ProcessorChecksum; 55 } EFI_CPU_MICROCODE_EXTENDED_TABLE; 56 57 typedef struct { 58 UINT32 Stepping : 4; 59 UINT32 Model : 4; 60 UINT32 Family : 4; 61 UINT32 Type : 2; 62 UINT32 Reserved1 : 2; 63 UINT32 ExtendedModel : 4; 64 UINT32 ExtendedFamily : 8; 65 UINT32 Reserved2 : 4; 66 } EFI_CPU_VERSION; 67 68 #define EFI_CPUID_SIGNATURE 0x0 69 #define EFI_CPUID_VERSION_INFO 0x1 70 #define EFI_CPUID_CACHE_INFO 0x2 71 #define EFI_CPUID_SERIAL_NUMBER 0x3 72 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000 73 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001 74 #define EFI_CPUID_BRAND_STRING1 0x80000002 75 #define EFI_CPUID_BRAND_STRING2 0x80000003 76 #define EFI_CPUID_BRAND_STRING3 0x80000004 77 78 #define EFI_MSR_IA32_PLATFORM_ID 0x17 79 #define EFI_MSR_IA32_APIC_BASE 0x1B 80 #define EFI_MSR_EBC_HARD_POWERON 0x2A 81 #define EFI_MSR_EBC_SOFT_POWERON 0x2B 82 #define BINIT_DRIVER_DISABLE 0x40 83 #define INTERNAL_MCERR_DISABLE 0x20 84 #define INITIATOR_MCERR_DISABLE 0x10 85 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C 86 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79 87 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B 88 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD 89 #define EFI_APIC_GLOBAL_ENABLE 0x800 90 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0 91 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000 92 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008 93 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004 94 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002 95 #define FAST_STRING_ENABLE_BIT 0x00000001 96 97 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200 98 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F 99 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF 100 #define EFI_CACHE_MTRR_VALID 0x800 101 #define EFI_CACHE_FIXED_MTRR_VALID 0x400 102 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 103 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF 104 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000 105 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF 106 107 #define EFI_IA32_MTRR_FIX64K_00000 0x250 108 #define EFI_IA32_MTRR_FIX16K_80000 0x258 109 #define EFI_IA32_MTRR_FIX16K_A0000 0x259 110 #define EFI_IA32_MTRR_FIX4K_C0000 0x268 111 #define EFI_IA32_MTRR_FIX4K_C8000 0x269 112 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A 113 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B 114 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C 115 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D 116 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E 117 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F 118 119 #define EFI_IA32_MCG_CAP 0x179 120 #define EFI_IA32_MCG_CTL 0x17B 121 #define EFI_IA32_MC0_CTL 0x400 122 #define EFI_IA32_MC0_STATUS 0x401 123 124 #define EFI_IA32_PERF_STATUS 0x198 125 #define EFI_IA32_PERF_CTL 0x199 126 127 #define EFI_CACHE_UNCACHEABLE 0 128 #define EFI_CACHE_WRITECOMBINING 1 129 #define EFI_CACHE_WRITETHROUGH 4 130 #define EFI_CACHE_WRITEPROTECTED 5 131 #define EFI_CACHE_WRITEBACK 6 132 133 // 134 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number 135 // 136 #define EfiMakeCpuVersion(f, m, s) \ 137 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s))) 138 139 VOID 140 EFIAPI 141 EfiHalt ( 142 VOID 143 ); 144 145 /*++ 146 Routine Description: 147 Halt the Cpu 148 Arguments: 149 None 150 Returns: 151 None 152 --*/ 153 VOID 154 EFIAPI 155 EfiWbinvd ( 156 VOID 157 ); 158 159 /*++ 160 Routine Description: 161 Write back and invalidate the Cpu cache 162 Arguments: 163 None 164 Returns: 165 None 166 --*/ 167 VOID 168 EFIAPI 169 EfiInvd ( 170 VOID 171 ); 172 173 /*++ 174 Routine Description: 175 Invalidate the Cpu cache 176 Arguments: 177 None 178 Returns: 179 None 180 --*/ 181 VOID 182 EFIAPI 183 EfiCpuid ( 184 IN UINT32 RegisterInEax, 185 OUT EFI_CPUID_REGISTER *Regs 186 ); 187 188 /*++ 189 Routine Description: 190 Get the Cpu info by excute the CPUID instruction 191 Arguments: 192 RegisterInEax: -The input value to put into register EAX 193 Regs: -The Output value 194 Returns: 195 None 196 --*/ 197 198 VOID 199 EFIAPI 200 EfiCpuidExt ( 201 IN UINT32 RegisterInEax, 202 IN UINT32 CacheLevel, 203 OUT EFI_CPUID_REGISTER *Regs 204 ) 205 /*++ 206 Routine Description: 207 When RegisterInEax != 4, the functionality is the same as EfiCpuid. 208 When RegisterInEax == 4, the function return the deterministic cache 209 parameters by excuting the CPUID instruction 210 Arguments: 211 RegisterInEax: - The input value to put into register EAX 212 CacheLevel: - The deterministic cache level 213 Regs: - The Output value 214 Returns: 215 None 216 --*/ 217 ; 218 219 UINT64 220 EFIAPI 221 EfiReadMsr ( 222 IN UINT32 Index 223 ); 224 225 /*++ 226 Routine Description: 227 Read Cpu MSR 228 Arguments: 229 Index: -The index value to select the register 230 231 Returns: 232 Return the read data 233 --*/ 234 VOID 235 EFIAPI 236 EfiWriteMsr ( 237 IN UINT32 Index, 238 IN UINT64 Value 239 ); 240 241 /*++ 242 Routine Description: 243 Write Cpu MSR 244 Arguments: 245 Index: -The index value to select the register 246 Value: -The value to write to the selected register 247 Returns: 248 None 249 --*/ 250 UINT64 251 EFIAPI 252 EfiReadTsc ( 253 VOID 254 ); 255 256 /*++ 257 Routine Description: 258 Read Time stamp 259 Arguments: 260 None 261 Returns: 262 Return the read data 263 --*/ 264 VOID 265 EFIAPI 266 EfiDisableCache ( 267 VOID 268 ); 269 270 /*++ 271 Routine Description: 272 Writing back and invalidate the cache,then diable it 273 Arguments: 274 None 275 Returns: 276 None 277 --*/ 278 VOID 279 EFIAPI 280 EfiEnableCache ( 281 VOID 282 ); 283 284 /*++ 285 Routine Description: 286 Invalidate the cache,then Enable it 287 Arguments: 288 None 289 Returns: 290 None 291 --*/ 292 UINT32 293 EFIAPI 294 EfiGetEflags ( 295 VOID 296 ); 297 298 /*++ 299 Routine Description: 300 Get Eflags 301 Arguments: 302 None 303 Returns: 304 Return the Eflags value 305 --*/ 306 VOID 307 EFIAPI 308 EfiDisableInterrupts ( 309 VOID 310 ); 311 312 /*++ 313 Routine Description: 314 Disable Interrupts 315 Arguments: 316 None 317 Returns: 318 None 319 --*/ 320 VOID 321 EFIAPI 322 EfiEnableInterrupts ( 323 VOID 324 ); 325 326 /*++ 327 Routine Description: 328 Enable Interrupts 329 Arguments: 330 None 331 Returns: 332 None 333 --*/ 334 335 336 VOID 337 EFIAPI 338 EfiCpuVersion ( 339 IN UINT16 *FamilyId, OPTIONAL 340 IN UINT8 *Model, OPTIONAL 341 IN UINT8 *SteppingId, OPTIONAL 342 IN UINT8 *Processor OPTIONAL 343 ) 344 /*++ 345 346 Routine Description: 347 Extract CPU detail version infomation 348 349 Arguments: 350 FamilyId - FamilyId, including ExtendedFamilyId 351 Model - Model, including ExtendedModel 352 SteppingId - SteppingId 353 Processor - Processor 354 355 --*/ 356 ; 357 358 #endif 359
